Building Automation Systems

The ADIN1200 is a low power, single-port, 10 Mbps and 100 Mbps Ethernet transceiver with low latency specifications designed for industrial Ethernet applications.

This design integrates an energy efficient Ethernet (EEE) physical layer device (PHY) core with all associated common analog circuitry, input and output clock buffering, management interface and subsystem registers, and media access control (MAC) interface and control logic to manage the reset, clock control and pin configuration.

The ADIN1200 is available in a 5 mm × 5 mm, 32-lead lead frame chip scale package (LFCSP) and can operate with a single 3.3 V supply, assuming the use of a 3.3 V MAC interface supply. For maximum flexibility in system level design, a separate VDDIO supply enables the management data input/output (MDIO) and MAC interface supply voltages to be configured independently of the other circuitry on the ADIN1200 allowing operation at 1.8 V, 2.5 V, or 3.3 V. At power-up, the ADIN1200 is held in hardware reset until each of the supplies has crossed its minimum rising threshold value and the power is considered good. Brownout protection is provided by monitoring the supplies to detect if one or more of them drops below a minimum falling threshold and holding the device in hardware reset until the power supplies return and satisfy the power-on-reset (POR) circuit.

The MII management interface (also referred to as MDIO interface) provides a 2-wire serial interface between a host processor or MAC and the ADIN1200, allowing access to control and status information in the PHY core management registers. The interface is compatible with both IEEE^® 802.3^™ Standard Clause 22 and Clause 45 management frame structures.

The ADIN1200 can support cable lengths up to 180 meters.

Note that throughout this data sheet, multifunction pins, such as XTAL_I/CLK_IN/REF_CLK, are referred to either by the entire pin name or by a single function of the pin, for example, XTAL_I, when only that function is relevant.

Applications

• Industrial automation
• Process control
• Factory automation
• Robotics and motion Control
• Building automation
• Test and Measurement
• Industrial internet of things (IoT)

The ADIN1300 is a low power, single port, Gigabit Ethernet transceiver with low latency and power consumption specifications primarily designed for industrial Ethernet applications.

This design integrates an energy efficient Ethernet (EEE) physical layer device (PHY) core with all associated common analog circuitry, input and output clock buffering, management interface and subsystem registers, and MAC interface and control logic to manage the reset and clock control and pin configuration.

The ADIN1300 is available in a 6 mm × 6 mm, 40-lead lead frame chip scale package (LFCSP). The device operates with a minimum of 2 power supplies, 0.9 V and 3.3 V, assuming the use of a 3.3 V MAC interface supply. For maximum flexibility in system level design, a separate VDDIO supply enables the management data input/output (MDIO) and MAC interface supply voltages to be configured independently of the other circuitry on the ADIN1300, allowing operation at 1.8 V, 2.5 V, or 3.3 V. At power-up, the ADIN1300 is held in hardware reset until each of the supplies has crossed its minimum rising threshold value. Brown-out protection is provided by monitoring the supplies to detect if one or more supply drops below a minimum falling threshold (see Table 17 on the datasheet), and holding the device in hardware reset until the power supplies return and satisfy the power-on reset (POR) circuit.

The MII management interface (also referred to as MDIO interface) provides a 2-wire serial interface between a host processor or MAC (also known as management station (STA)) and the ADIN1300, allowing access to control and status information in the PHY core management registers. The interface is compatible with both the IEEE 802.3 Standard Clause 22 and Clause 45 management frame structures.

The ADIN1300 can support cable lengths up to 150 meters at Gigabit speeds and 180 meters when operating at 100 Mbps or 10 Mbps.

Applications

• Industrial automation
• Process control
• Factory automation
• Robotics/Motion Control
• Building automation
• Test and Measurement
• Industrial IoT

The fido5100 and fido5200 (REM switch) are programmable IEEE 802.3 10 Mbps/100 Mbps Ethernet Internet Protocol Version 6 (IPv6) and Internet Protocol Version 4 (IPv4) switches that support virtually any Layer 2 or Layer 3 protocol. The switches are personalized to support the desired protocol by firmware that is downloaded from a host processor.

The firmware is contained in the real-time Ethernet multiprotocol (REM) switch driver and is downloaded at power-up. The REM switch can be ready for network data operation in less than 4 ms to support fast startup and quick connect type network functionality. The REM switch devices have the same signal assignments as defined in this data sheet.

The fido5100 supports the following protocols: PROFINET real time (RT) and isochronous real time (IRT), EtherNet/IP with and without device level ring (DLR), Modbus TCP, and POWERLINK.

The fido5200 supports the following protocols: EtherCAT and all protocols defined for the fido5100.

The REM switch is intended for use with a host processor. Network operation is handled using the functions and services provided in the REM switch driver. The host processor can implement any protocol stack by integrating it with the REM switch driver. An example application is shown in Figure 11.

The REM switches are available in a 144-ball chip scale package ball grid array (CSP_BGA) package.

Note that throughout this data sheet, multifunction pins, such as A02/ALE, are referred to either by the entire pin name or by a single function of the pin, for example, ALE, when only that function is relevant.

Applications

• Industrial automation
  
  • Process control
  • Managed Ethernet switch

The fido5100 and fido5200 (REM switch) are programmable IEEE 802.3 10 Mbps/100 Mbps Ethernet Internet Protocol Version 6 (IPv6) and Internet Protocol Version 4 (IPv4) switches that support virtually any Layer 2 or Layer 3 protocol. The switches are personalized to support the desired protocol by firmware that is downloaded from a host processor.

The firmware is contained in the real-time Ethernet multiprotocol (REM) switch driver and is downloaded at power-up. The REM switch can be ready for network data operation in less than 4 ms to support fast startup and quick connect type network functionality. The REM switch devices have the same signal assignments as defined in this data sheet.

The fido5100 supports the following protocols: PROFINET real time (RT) and isochronous real time (IRT), EtherNet/IP with and without device level ring (DLR), Modbus TCP, and POWERLINK.

The fido5200 supports the following protocols: EtherCAT and all protocols defined for the fido5100.

The REM switch is intended for use with a host processor. Network operation is handled using the functions and services provided in the REM switch driver. The host processor can implement any protocol stack by integrating it with the REM switch driver. An example application is shown in Figure 11.

The REM switches are available in a 144-ball chip scale package ball grid array (CSP_BGA) package.

Note that throughout this data sheet, multifunction pins, such as A02/ALE, are referred to either by the entire pin name or by a single function of the pin, for example, ALE, when only that function is relevant.

Applications

• Industrial automation
  
  • Process control
  • Managed Ethernet switch

The ADuCM4050 microcontroller unit (MCU) is an ultra low power integrated microcontroller system with integrated power management for processing, control, and connectivity. The MCU system is based on the ARM^® Cortex^®-M4F processor. The MCU also has a collection of digital peripherals, embedded static random access memory (SRAM) and embedded flash memory, and an analog subsystem that provides clocking, reset, and power management capabilities in addition to an analog-to-digital converter (ADC) subsystem.

This data sheet describes the ARM Cortex-M4F core and memory architecture used on the ADuCM4050 MCU. It does not provide detailed programming information about the ARM processor.

The system features include an up to 52 MHz ARM Cortex-M4F processor, 512 kB of embedded flash memory with error correction code (ECC), an optional 4 kB cache for lower active power, and 128 kB system SRAM with parity. The ADuCM4050 features a power management unit (PMU), multilayer advanced microcontroller bus architecture (AMBA) bus matrix, central direct memory access (DMA) controller, and beeper interface.

The ADuCM4050 features cryptographic hardware supporting advanced encryption standard (AES)-128 and AES-256 with secure hash algorithm (SHA)-256 and the following modes: electronic code book (ECB), cipher block chaining (CBC), counter (CTR), and cipher block chaining-message authentication code (CCM/CCM*) modes.

The ADuCM4050 has protected key storage with key wrap/ unwrap, and keyed hashed message authentication code (HMAC) with key unwrap.

The ADuCM4050 supports serial port (SPORT), serial peripheral interface (SPI), I²C, and universal asynchronous receiver/ transmitter (UART) peripheral interfaces.

The ADuCM4050 features a real-time clock (RTC), general-purpose and watchdog timers, and programmable general-purpose input/output (GPIO) pins. There is a hardware cyclic redundancy check (CRC) calculator with programmable generator polynomial. The device also features a power on reset (POR) and power supply monitor (PSM), a 12-bit successive approximation register (SAR) ADC, a red/green/blue (RGB) timer for driving RGB LED, and a true random number generator (TRNG).

To support low dynamic and hibernate power management, the ADuCM4050 MCU provides a collection of power modes and features such as dynamic- and software-controlled clock gating and power gating.

For full details on the ADuCM4050 MCU, refer to the ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference.

Product Highlights

1. Ultra low power consumption.
2. Robust operation.
3. Full voltage monitoring in deep sleep modes.
4. ECC support on flash.
5. Parity error detection on SRAM memory.
6. Leading edge security.
7. Fast encryption provides read protection to user algorithms.
8. Write protection prevents device reprogramming by unauthorized code.
9. Failure detection of 32 kHz low frequency external crystal oscillator (LFXTAL) via interrupt.
10. SensorStrobe^™ for precise time synchronized sampling of external sensors. Works in hibernate mode, resulting in drastic current reduction in system solutions. Current consumption reduces by 10 times when using, for example, the ADXL363 accelerometer. Software intervention is not required after setup. No pulse drift due to software execution.

Applications

• Internet of Things (IoT)
• Smart agriculture, smart building, smart metering, smart city, smart machine, and sensor network
• Wearables
• Fitness and clinical
• Machine learning and neural networks