Digital Cabin Experience

The Automotive Audio Bus (A²B^®) provides a multichannel, I²S/TDM link over distances of up to 15 m between nodes. It embeds bidirectional synchronous pulse-code modulation (PCM) data (for example, digital audio), clock, and synchronization signals onto a single differential wire pair. A²B supports a direct point to point connection and allows multiple, daisy-chained nodes at different locations to contribute and/or consume time division multiplexed (TDM) channel content.

A²B is a single-master, multiple-slave system where the transceiver at the host controller is the master. The master generates clock, synchronization, and framing for all slave nodes. The master A²B transceiver is programmable over a control port (I²C) for configuration and read back. An extension of this control port is embedded in the A²B data stream, which grants direct access of registers and status information on slave transceivers as well as I²C to I²C communication over distance.

The transceiver can connect directly to general-purpose digital signal processors (DSPs), field-programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), microphones, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and codecs through a multichannel I²S/TDM interface. It also provides a pulse density modulation (PDM) interface for direct connection of up to four PDM digital microphones.

Finally, the transceiver also supports an A²B bus powering feature, where the master node supplies voltage and current to the slave nodes over the same daisy-chained, twisted pair wire cable as used for the communication link.

¹ N/A means not applicable.
² PDM microphones must be connected to the DRX0/IO5 pin.

Applications

• Audio communication link
• Microphone arrays
  
  • Beamforming
  • Hands free and in car communication
• Active and road noise cancellation
• Audio/video conferencing systems

The Automotive Audio Bus (A²B^®) provides a multichannel, I²S/TDM link over distances of up to 15 m between nodes. It embeds bidirectional synchronous pulse-code modulation (PCM) data (for example, digital audio), clock, and synchronization signals onto a single differential wire pair. A²B supports a direct point to point connection and allows multiple, daisy-chained nodes at different locations to contribute and/or consume time division multiplexed (TDM) channel content.

A²B is a single-master, multiple-slave system where the transceiver at the host controller is the master. The master generates clock, synchronization, and framing for all slave nodes. The master A²B transceiver is programmable over a control port (I²C) for configuration and read back. An extension of this control port is embedded in the A²B data stream, which grants direct access of registers and status information on slave transceivers as well as I²C to I²C communication over distance.

The transceiver can connect directly to general-purpose digital signal processors (DSPs), field-programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), microphones, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and codecs through a multichannel I²S/TDM interface. It also provides a pulse density modulation (PDM) interface for direct connection of up to four PDM digital microphones.

Finally, the transceiver also supports an A²B bus powering feature, where the master node supplies voltage and current to the slave nodes over the same daisy-chained, twisted pair wire cable as used for the communication link.

¹ N/A means not applicable.
² PDM microphones must be connected to the DRX0/IO5 pin.

Applications

• Audio communication link
• Microphone arrays
  
  • Beamforming
  • Hands free and in car communication
• Active and road noise cancellation
• Audio/video conferencing systems

The Automotive Audio Bus (A²B^®) provides a multichannel, I²S/TDM link over distances of up to 15 m between nodes. It embeds bidirectional synchronous pulse-code modulation (PCM) data (for example, digital audio), clock, and synchronization signals onto a single differential wire pair. A²B supports a direct point to point connection and allows multiple, daisy-chained nodes at different locations to contribute and/or consume time division multiplexed (TDM) channel content.

A²B is a single-master, multiple-slave system where the transceiver at the host controller is the master. The master generates clock, synchronization, and framing for all slave nodes. The master A²B transceiver is programmable over a control port (I²C) for configuration and read back. An extension of this control port is embedded in the A²B data stream, which grants direct access of registers and status information on slave transceivers as well as I²C to I²C communication over distance.

The transceiver can connect directly to general-purpose digital signal processors (DSPs), field-programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), microphones, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and codecs through a multichannel I²S/TDM interface. It also provides a pulse density modulation (PDM) interface for direct connection of up to four PDM digital microphones.

Finally, the transceiver also supports an A²B bus powering feature, where the master node supplies voltage and current to the slave nodes over the same daisy-chained, twisted pair wire cable as used for the communication link.

¹ N/A means not applicable.
² PDM microphones must be connected to the DRX0/IO5 pin.

Applications

• Audio communication link
• Microphone arrays
  
  • Beamforming
  • Hands free and in car communication
• Active and road noise cancellation
• Audio/video conferencing systems

The ADSP-SC57x/ADSP-2157x processors are members of the SHARC^® family of products. The ADSP-SC57x processor is based on the SHARC+^® dual-core and the arm^® Cortex^®-A5 core. The ADSP-SC57x/ADSP-2157x SHARC processors are members of the single-instruction, multiple data (SIMD) SHARC family of digital signal processors (DSPs) that feature Analog Devices Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with large on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). New additions to the SHARC+ core include cache enhancements and branch prediction, while maintaining instruction set compatibility to previous SHARC products.

By integrating a set of industry leading system peripherals and memory, the arm^® Cortex-A5 and SHARC processor is the platform of choice for applications that require programmability similar to reduced instruction set computing (RISC), multimedia support, and leading edge signal processing in one integrated package. These applications span a wide array of markets, including automotive, professional audio, and industrial-based applications that require high floating-point performance.

The ADSP-SC57x/ADSP-2157x processors are members of the SHARC^® family of products. The ADSP-SC57x processor is based on the SHARC+^® dual-core and the arm^® Cortex^®-A5 core. The ADSP-SC57x/ADSP-2157x SHARC processors are members of the single-instruction, multiple data (SIMD) SHARC family of digital signal processors (DSPs) that feature Analog Devices Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with large on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). New additions to the SHARC+ core include cache enhancements and branch prediction, while maintaining instruction set compatibility to previous SHARC products.

By integrating a set of industry leading system peripherals and memory, the arm^® Cortex-A5 and SHARC processor is the platform of choice for applications that require programmability similar to reduced instruction set computing (RISC), multimedia support, and leading edge signal processing in one integrated package. These applications span a wide array of markets, including automotive, professional audio, and industrial-based applications that require high floating-point performance.

The ADAU1462/ADAU1466 are automotive qualified audio processors that far exceed the digital signal processing capabilities of earlier SigmaDSP^® devices. They are pin and register compatible with each other, as well as with the ADAU1450/ADAU1451/ADAU1452 SigmaDSP processors. The restructured hardware architecture is optimized for efficient audio processing. The audio processing algorithms support a seamless combination of stream processing (sample by sample), multirate processing, and block processing paradigms. The SigmaStudio™ graphical programming tool enables the creation of signal processing flows that are interactive, intuitive, and powerful. The enhanced digital signal processor (DSP) core architecture enables some types of audio processing algorithms to be executed using significantly fewer instructions than were required on previous SigmaDSP generations, leading to vastly improved code efficiency.

The 1.2 V, 32-bit DSP core can run at frequencies of up to 294.912 MHz and execute up to 6144 SIMD instructions per sample at the standard sample rate of 48 kHz. Powerful clock generator hardware, including a flexible phase-locked loop (PLL) with multiple fractional integer outputs, supports all industry standard audio sample rates. Nonstandard rates over a wide range can generate up to 15 sample rates simultaneously. These clock generators, along with the on board asynchronous sample rate converters (ASRCs) and a flexible hardware audio routing matrix, make the ADAU1462/ADAU1466 ideal audio hubs that greatly simplify the design of complex multirate audio systems.

The ADAU1462/ADAU1466 interface with a wide range of analog-to-digital converters (ADCs), digital-to-analog converters (DACs), digital audio devices, amplifiers, and control circuitry with highly configurable serial ports, I²C, serial peripheral interface (SPI), Sony/Philips Digital Interconnect Format (S/PDIF) interfaces, and multipurpose input/output (I/O) pins. Dedicated decimation filters can decode the pulse code modulation (PDM) output of up to four MEMS microphones.

Independent slave and master I²C/SPI control ports allow the ADAU1462/ADAU1466 to be programmed and controlled by an external master device such as a microcontroller, and to program and control slave peripherals directly. Self boot functionality and the master control port enable complex standalone systems.

The power efficient DSP core can execute at high computational loads while consuming only a few hundred milliwatts (mW) in typical conditions. This relatively low power consumption and small footprint make the ADAU1462/ADAU1466 ideal replacements for large, general-purpose DSPs that consume more power at the same processing load.

Applications

• Automotive audio processing
  
  • Head units
  • Distributed processors
  • Rear seat entertainment systems
  • Trunk amplifiers
• Commercial and professional audio processing

The ADAU1463/ADAU1467 are automotive qualified audio processors that far exceed the digital signal processing capabilities of earlier SigmaDSP^® devices. They are pin and register compatible with each other, as well as with the ADAU1450/ADAU1451/ADAU1452 SigmaDSP^® processors. The restructured hardware architecture is optimized for efficient audio processing. The audio processing algorithms support a seamless combination of stream processing (sample-by-sample), multirate processing, and block processing paradigms. The SigmaStudio^® graphical programming tool enables the creation of signal processing flows that are interactive, intuitive, and powerful. The enhanced digital signal processor (DSP) core architecture enables some types of audio processing algorithms to be executed using significantly fewer instructions than were required on previous SigmaDSP generations, leading to vastly improved code efficiency.

The 1.2 V, 32-bit DSP core can run at frequencies of up to 294.912 MHz and execute up to 6144 single instruction, multiple data (SIMD) instructions per sample at the standard sample rate of 48 kHz. Powerful clock generator hardware, including a flexible phase-locked loop (PLL) with multiple fractional integer outputs, supports all industry standard audio sample rates. Nonstandard rates over a wide range can generate up to 15 sample rates simultaneously. These clock generators, along with the on-board asynchronous sample rate converters (ASRCs) and a flexible hardware audio routing matrix, make the ADAU1463/ADAU1467 ideal audio hubs that greatly simplify the design of complex multirate audio systems.

The ADAU1463/ADAU1467 have four input serial ports and four output serial ports. Each device has an asynchronous clock domain capable of operating as either a bit clock and frame sync master or slave. Each of the serial ports supports multiple data lines. The eight SDATAIOx pins each can be associated with any of the four input or four output serial ports. The use of assignable data pins allows a serial port to transmit or receive additional channels of audio data using a single bit clock and frame clock. Each of the supplemental data pins can carry from two to eight channels of serial audio. This flexible configuration provides more channels of audio input/output (I/O) without the need to run serial ports at high speed, and enables systems with additional serial audio peripherals. These expanded serial audio ports, along with the clock generators, the on-board asynchronous sample rate converters (ASRCs), and a flexible hardware audio routing matrix make the ADAU1463/ ADAU1467 ideal audio hubs that greatly simplify the design of complex, multirate audio systems.

The ADAU1463/ADAU1467 interface with a wide range of analog-to-digital converters (ADCs), digital-to-analog converters (DACs), digital audio devices, amplifiers, and control circuitry with highly configurable serial ports, I²C, serial peripheral interface (SPI), Sony/Philips Digital Interconnect Format (S/PDIF) interfaces, and multipurpose I/O pins. Dedicated decimation filters can decode the pulse density modulation (PDM) output of up to four MEMS microphones.

Independent slave and master I²C/SPI control ports allow the ADAU1463/ADAU1467 to be programmed and controlled by an external master device such as a microcontroller, and to program and control slave peripherals directly. Self boot functionality and the master control port enable complex standalone systems.

Note that throughout this data sheet, multifunction pins, such as SDATAIO4/MP20, are referred to either by the entire pin name or by a single function of the pin, for example, MP20, when only that function is relevant.

Applications

• Automotive audio processing
  • Head units
  • Distributed amplifiers
  • Rear seat entertainment systems
  • Trunk amplifiers
• Commercial and professional audio processing

The ADV7282A has the same pinout as and is software compatible with the ADV7282. The mobile industry processor interface (MIPI^®) model of the ADV7282A (ADV7282A-M) has the same pinout as and is software compatible with the ADV7282-M.

All features, functionality, and specifications are shared by the ADV7282A and the ADV7282A-M, unless otherwise noted.

The ADV7282A is a versatile one-chip, multiformat video decoder that automatically detects standard analog baseband video signals and converts them into YCrCb 4:2:2 component video data streams.

The analog input of the ADV7282A features an input mux (4-channel on ADV7282A, 6-channel on ADV7282A-M), a single 10-bit analog-to-digital converter (ADC) and an on-chip differential to single-ended converter to accommodate the direct connection of differential, pseudo differential, or single-ended CVBS without the need for external amplifier circuitry.

The standard definition processor (SDP) in the ADV7282A automatically detects PAL, NTSC and SECAM standards in the form of composite, S-Video (Y/C) and component. The analog video is converted into a 4:2:2 component video data stream that is output either via an 8-bit ITU-R BT.656 standard-compatible interface (ADV7282A) or via a MIPI CSI-2 Tx (hereafter referred to as MIPI Tx) interface (ADV7282A-M). The ADV7282A also feature a deinterlacer for interlaced to progressive (I²P) conversion.

The ADV7282A offers short to battery (STB) diagnostic sense inputs and general-purpose outputs.

The ADV7282A is provided in a space-saving LFCSP surface-mount, RoHS compliant package. The ADV7282A is rated over the −40°C to +105°C temperature range, making it ideal for automotive applications.

The ADV7282A must be configured in accordance with the I²C writes provided in the evaluation board script files.

Applications

• Advanced driver assistance
• Automotive infotainment
• DVRs for video security
• Media players

The ADV7613 is a high quality, low power, single-input HDMI to LVDS display bridge. It incorporates an HDMI capable receiver that supports up to 1080p, 60 Hz.

The HDMI port has dedicated 5 V detect and hot plug assert pins. The HDMI receiver also includes an integrated equalizer that ensures the robust operation of the interface with long cables.

The ADV7613 has an audio output port for the audio data extracted from the HDMI stream. HDMI audio formats include super audio CD (SACD) via Direct Stream Digital^® (DSD) and HBR. The HDMI receiver has an advanced mute controller that prevents audible extraneous noise in the audio output.

The ADV7613 contains a component processor (CP) that processes the video signals from the HDMI receiver. It provides features such as contrast, brightness and saturation adjustments, STDI detection block, free run, and synchronization alignment controls.

The LVDS encoder can package data into 6-bit or 8-bit non-dc balanced OpenLDI mapping or 8-bit VESA mapping. The ADV7613 can output 24-bit OpenLDI data via dual-channel LVDS transmitters, up to a maximum resolution of 1080p, 60 Hz received at the input. The maximum output clock supported by a single LVDS output port is 92 MHz.

The ADV7613 is offered in an automotive grade and a consumer grade. The operating temperature range is −40°C to +85°C.

Fabricated in an advanced CMOS process, the ADV7613 is provided in a 9 mm × 9 mm, 100-ball CSP_BGA, RoHS-compliant package.

Applications

• Projectors
• Automotive infotainment headunits
• Automotive infotainment displays
• Digital signage

Complete technical specifications are available for the C²B transmitters and receivers. Contact c2b_web_support@analog.com to complete the nondisclosure agreement (NDA) required to receive additional product information.  

General

• C²B transmits video and bidirectional control data over low cost, un-shielded differential pair cable
• −40°C to +105°C temperature grade
• 32-lead and 40-lead LFCSP packages
• AEC-Q100 qualified for automotive applications

Applications

• Automotive camera modules
• Automotive camera ECUs
• Automotive infotainment head units

Electric Vehicles (EV) and Hybrid Electric Vehicles (HEV) are almost silent when travelling at low speed and pose a significant hazard to blind pedestrians. It has been mandated in most regions that EVs and HEVs emit an external sound when travelling at low speeds. ADI have developed an Electric Vehicle Warning Sound System (EVWSS) reference design that creates an engine sound or series of sounds designed to alert pedestrians to the presence of an EV/HEV/PHEV. Warning sounds can be initiated by the driver (similar to the sound from a car horn, but less urgent) but must be automatically enabled at low speeds.

Analog Devices, Inc. is offering two different solutions: For advanced applications where customers may want an in-cabin engine sound for their EV as well as an external engine sound, ADI have developed a solution based on the ADSP-BF706. For entry-level systems, ADI have developed a solution based on the ADAU1450 Sigma DSP. Both systems can synthesize the sound, provide dynamic volume control, frequency shifting and other parameters.