Electronic Surveillance and Countermeasures

The circuit shown in Figure 1 is an accurate 40 GHz, microwave power meter with a 45 dB range that requires only two components. The RF detector has an innovative detector cell using Schottky diodes followed by an analog linearization circuit. A low power, 12-bit, 1 MSPS analog-to-digital converter (ADC) provides a digital output on a serial peripheral interface (SPI) port.

A simple calibration routine is run before measurement operation, at the particular RF frequency of interest. The user can then operate the system in measurement mode. When in measurement mode, the CN-0366 Evaluation Software displays the calibrated RF input power that is applied at the input of the detector in units of dBm.

The total power dissipation of this circuit is less than 9 mW on a single 5 V supply.

This circuit is a frequency selective, radio frequency (RF) detector that offers 90 dB of detection range from 35 MHz to 4.4 GHz. Unlike a standalone detector that does not discriminate between signals in the frequency spectrum, this circuit has the ability to focus on a narrow band of frequencies, providing enhanced performance over the specified range. The detector circuit is rms responding and stable vs. temperature and frequency, making it an attractive solution for applications that require precise frequency, selective RF power measurement. The circuit also demonstrates strong immunity to unwanted blockers. Figure 1 shows a simplified schematic of the circuit.

The circuit, shown in Figure 1, is a 65 MHz bandwidth receiver front end based on the ADL5565 ultrahigh dynamic range differential amplifier driver and the 11-bit, 200 MSPS AD6657A quad IF receiver.

The fourth-order Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and IF receiver. The total insertion loss due the filter network and other resistive components is only 2.0 dB. The overall circuit has a bandwidth of 65 MHz, with the low-pass filter having a 1 dB bandwidth of 190 MHz and a 3 dB bandwidth of 210 MHz. The pass-band flatness is 1dB.

The circuit is optimized to process a 65 MHz bandwidth IF signal centered at 140 MHz with a sampling rate of 184.32 MSPS. The SNR and SFDR measured with a 140 MHz analog input across the 65 MHz band are 70.1 dBFS and 80.9 dBc, respectively.

The circuit shown in Figure 1 is a 16-bit, 250 MSPS, narrow-band, high IF receiver front end with an optimum interface between the ADL5565 differential amplifier and the AD9467 ADC.

The AD9467 is a buffered input 16-bit, 200 MSPS or 250 MSPS ADC with SNR performance of approximately 75.5 dBFS and SFDR performance between 95 dBFS and 98 dBFS. The ADL5565 differential amplifier is suitable for driving IF sampling ADCs because of its high input bandwidth, low distortion, and high output linearity.

This circuit note describes a systematic procedure for designing the interface circuit and the antialiasing filter that maintains high performance and ensures minimal signal loss. A resonant approach is used to design a maximally flat Butterworth fourth-order band-pass filter with a center frequency of 200 MHz.

The circuit, shown in Figure 1, is a wideband receiver front end based on the ADA4960-1 ultralow noise differential amplifier driver and the AD9434 12-bit, 500 MSPS analog-to-digital converter.

The third-order Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and ADC. The total insertion loss due to the filter network, transformer, and other resistive components is only 1.2 dB.

The overall circuit has a bandwidth of 290 MHz with a pass-band flatness of 1 dB. The SNR and SFDR measured with a 140 MHz analog input are 64.1 dBFS and 70.4 dBc, respectively.

The circuit, shown in Figure 1, is a wideband receiver front end based on the the ADL5562 ultralow noise differential amplifier driver and the AD9467 16-bit, 250 MSPS analog-to-digital converter.

The third-order Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and ADC. The total insertion loss due to the filter network and other components is only 1.8 dB.

The overall circuit has a bandwidth of 152 MHz with a pass band flatness of 1 dB. The SNR and SFDR measured with a 120 MHz analog input are 72.6 dBFS and 82.2 dBc, respectively.

Many systems require low jitter multiple system clocks for mixed signal processing and timing. The circuit shown in Figure 1 interfaces the ADF4351 integrated phase-locked loop (PLL) and voltage-controlled oscillator (VCO) to the ADCLK948, which provides up to eight differential, low voltage, positive emitter coupled logic (LVPECL) outputs from one differential output of the ADF4351.

Modern digital systems often require many high quality clocks at logic levels that are different from the logic level of the clock source. Extra buffering may be required to guarantee accurate distribution to other circuit components without loss of integrity. The interface between the ADF4351 clock source ADCLK948 clock fanout buffer is described, and measurements show that the additive jitter associated with the clock fanout buffer is 75 fs rms.

The circuit, shown in Figure 1, is a narrow, band-pass receiver front end based on the ADL5565 ultralow noise differential amplifier driver and the AD9642 14-bit, 250 MSPS analog-to-digital converter (ADC).

The third-order, Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and ADC. The total insertion loss due to the filter network and other components is only 5.8 dB.

The overall circuit has a bandwidth of 18 MHz with a pass-band flatness of 3 dB. The signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) measured with a 127 MHz analog input are 71.7 dBFS and 92 dBc, respectively. The sampling frequency is 205 MSPS, thereby positioning the IF input signal in the second Nyquist zone between 102.5 MHz and 205 MHz.

This circuit is a complete implementation of the analog portion of a broadband direct conversion transmitter (analog baseband in, RF out). RF frequencies from 500 MHz to 4.4 GHz are supported using a phase-locked loop (PLL) with a broadband, integrated voltage controlled oscillator (VCO). Harmonic filtering of the local oscillator (LO) from the PLL ensures excellent quadrature accuracy, sideband suppression, and low EVM.

Low noise, low dropout regulators (LDOs) ensure that the power management scheme has no adverse impact on phase noise and EVM. This combination of components represents industry leading direct conversion transmitter performance over a frequency range of 500 MHz to 4.4 GHz.

This circuit uses the ADL5902 TruPwr^™ detector to measure the rms signal strength of RF signals with varying crest factors (peak-to-average ratio) over a dynamic range of approximately 65 dB and operates at frequencies from 50 MHz up to 9 GHz.

The measurement result is provided as serial data at the output of a 12-bit ADC (AD7466). A simple 4-point system calibration at ambient temperature is performed in the digital domain.

The interface between the RF detector and the ADC is straightforward, consisting of two signal scaling resistors and no active components. In addition, the ADL5902 internal 2.3 V reference voltage provides the supply and reference voltage for the micropower ADC. The AD7466 has no pipeline delay and is operated as a read-only SAR ADC.

The overall circuit achieves temperature stability of approximately ±0.5 dB.

Data is shown for the two devices operating over a −40°C to +85°C temperature range.

This circuit is a high performance, dual channel IF sampling receiver, also called a “main” and "diversity" receiver in base station terminology. The downconverting receiver uses a single IF frequency of 153.6 MHz and includes a dual downconverting mixer, digitally controlled dual VGA, dual ADC, and clock synthesizer. The circuit takes an incoming RF waveform and outputs a dual 14-bit resolution digital data stream. It is optimized for high frequency IF sampling and provides exceptional spurious-free dynamic range (SFDR) performance of 79.61 dBc with a sampling rate of 122.88 MSPS at the high gain setting.

The circuit shown in Figure 1 is an RF power measurement circuit that accurately measures the power from an RF signal source within a frequency range of 9 kHz to 6 GHz, and has a nominal input power range of 45 dBm (−30 dBm to +15 dBm).

This circuit constitutes a complete rms RF power meter in a tiny form factor that can be powered entirely from a 5 V USB power supply. The measurement signal chain consists of an rms responding RF power detector and a 12-bit, precision analog-to-digital converter (ADC). These devices are powered by a CMOS linear regulator which generates 3.3 V from the 5 V USB supply.

A simple calibration routine can be performed at multiple frequencies to compensate for any frequency response variation of the circuit. Calibration data is stored in a lookup table, which is referenced during the RF power measurement.

The circuit shown in Figure 1 accurately measures return loss in a wireless transmitter from 1 GHz to 28 GHz without any need for system calibration.

The design is implemented on a single circuit board using a nonreflective RF switch; a microwave RF detector; and a 12-bit, precision analog-to-digital converter (ADC). To evaluate the circuit over the widest possible frequency range, a dual-port directional coupler with SMA connectors was used instead of a narrow-band, surface-mount directional coupler.

The circuit measures return loss of up to 20 dB over an input power range of 25 dB (return losses in excess of 20 dB can be measured over a smaller input power range).

A unique feature of the circuit is that it calculates return loss using a simple ratio of the digitized voltages from the RF detector, thereby eliminating the need for system calibration.

The automatic gain control (AGC) circuit is useful in multiple applications such as amplitude stabilization of a synthesizer, controlling output power in a transmitter, or optimizing dynamic range in a receiver. The circuit shown in Figure 1 uses the ADL6010 detector, along with the HMC985A voltage variable attenuator (VVA) and the HMC635 RF amplifier, to provide automatic gain control over a wide range of input frequencies (20 GHz to 37.5 GHz) and amplitude. Circuit performance, as measured by the AGC figures of merit described in this circuit note, are very good between 20 GHz and 30 GHz. The overall gain of the circuit falls off above 30 GHz. However, improvements can be made over narrow bands by using matching techniques not explored in this circuit note.

The AGC circuit has applications in microwave instrumentation and radar-based measurement systems.

The circuit in Figure 1 is a true rms responding power detector using a variable gain amplifier (VGA) and an rms-responding power detector to provide an extremely wide detection range of approximately 95 dB. RMS detectors are useful in many applications such as receivers and transmitters where accurate measurement of signal power is required. Because the circuit measures rms power, it is suitable for use in systems with diverse or varying crest factors. Examples of such systems include GSM/EDGE, CDMA, WCDMA, TD-SCDMA and LTE based wireless base stations along with any system that uses QAM modulation.

The detection range of the ADL5902 rms detector is 65 dB and is extended to 95 dB by the addition of the linear-in-dB AD8368 VGA. The ADL5902 TADJ function is used to provide temperature stability for the complete circuit. A SAW filter is placed between the VGA to reduce noise and increase sensitivity. This also reduces the frequency range of the circuit to the pass-band range of the SAW filter.

This circuit is a complete implementation of the analog portion of a broadband direct conversion transmitter (analog baseband in, RF out). RF frequencies from 30 MHz to 2.2 GHz are supported by using a phase-locked loop (PLL) with a broadband integrated voltage controlled oscillator (VCO). Unlike modulators that use a divide-by-1 local oscillator (LO) stage (as described in CN-0285), harmonic filtering of the LO is not required.

To achieve optimum performance, the only requirement is that the LO inputs of the modulator be driven differentially. The ADF4351 provides differential RF outputs and is, therefore, an excellent match. This PLL-to-modulator interface is applicable to all I/Q modulators and I/Q demodulators that contain a 2XLO-based phase splitter. Low noise LDOs ensure that the power management scheme has no adverse impact on phase noise and error vector magnitude (EVM). This combination of components represents an industry-leading direct conversion transmitter performance over a frequency range of 30 MHz to 2.2 GHz. For frequencies above 2.2 GHz, it is recommended to use a divide-by-1 modulator, as described in CN-0285.

The circuit shown in Figure 1 is a 10 MHz to 6 GHz wideband active mixer with a direct interface to a frequency synthesizer-based low phase noise local oscillator (LO).

This circuit offers an optimum solution that is attractive in wideband applications that require frequency conversion to higher or lower frequencies. The two-chip circuit covers a broad LO frequency range from 35 MHz to 4400 MHz. The LO interface is simple and glueless, eliminating the need for a balun, matching network, and LO buffer. In addition, the mixer bias adjust function allows optimization of IP3, noise figure, and supply current based on the application requirements or on the size of the input signal.