Home Theater and Gaming

The ADSP-SC57x/ADSP-2157x processors are members of the SHARC^® family of products. The ADSP-SC57x processor is based on the SHARC+^® dual-core and the arm^® Cortex^®-A5 core. The ADSP-SC57x/ADSP-2157x SHARC processors are members of the single-instruction, multiple data (SIMD) SHARC family of digital signal processors (DSPs) that feature Analog Devices Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with large on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). New additions to the SHARC+ core include cache enhancements and branch prediction, while maintaining instruction set compatibility to previous SHARC products.

By integrating a set of industry leading system peripherals and memory, the arm^® Cortex-A5 and SHARC processor is the platform of choice for applications that require programmability similar to reduced instruction set computing (RISC), multimedia support, and leading edge signal processing in one integrated package. These applications span a wide array of markets, including automotive, professional audio, and industrial-based applications that require high floating-point performance.

The AD1939 is a high performance, single-chip codec that provides four analog-to-digital converters (ADCs) with differential input, and eight digital-to-analog converters (DACs) with differential output using the Analog Devices, Inc. patented multibit sigma-delta (Σ-Δ) architecture. An SPI port is included, allowing a microcontroller to adjust volume and many other parameters. The AD1939 operates from 3.3 V digital and analog supplies. The AD1939 is available in a 64-lead (differential output) LQFP package.

The AD1939 is designed for low EMI. This consideration is apparent in both the system and circuit design architectures. By using the on-board PLL to derive the master clock from the LR clock or from an external crystal, the AD1939 eliminates the need for a separate high frequency master clock and can also be used with a suppressed bit clock. The DACs and ADCs are designed using the latest Analog Devices continuous time architectures to further minimize EMI. By using 3.3 V supplies, power consumption is minimized, further reducing emissions.

Applications

The ADV7672 is a High-Definition Multimedia Interface (HDMI^®) transceiver with crosspoint matrix switch, video mirror, video split, and video merge capabilities.

The ADV7672 supports 40 Gbps fixed rate link (FRL) and 18 Gbps transition minimized differential signaling (TMDS) video rates and provides two independent HDMI receiver ports, two independent HDMI transmitter ports, two audio ports, and an enhanced audio return channel (eARC) interface.

Each HDMI receiver and transmitter supports 8k30 RGB/YCbCr 4:4:4 10-bit video, 8k60 YCbCr 4:2:0 10-bit high definition video, and 4k120 4:4:4 10-bit high frame rate video.

Each audio port can be independently configured as either an audio extraction or audio insertion port. The audio ports support 8-channel, 192 kHz, 24-bit pulse coded modulation (PCM) and compressed audio formats including high bitrate formats.

The eARC interface can be configured as either an eARC transmitter or an eARC receiver. The eARC interface supports 8-channel 192 kHz PCM audio and high bit rate audio (HBR) compressed audio formats including Dolby TrueHD^™ and DTS-HD^™. Audio return channel (ARC) is also supported on the eARC interface.

The ADV7672 supports display stream compression (DSC) 1.2a data passthrough and high dynamic range (HDR) metadata passthrough for HDMI dynamic HDR, HDR10+, and Dolby Vision^™.

The ADV7672 implements the High-bandwidth Digital Content Protection (HDCP) 2.3 specification to protect the delivery of premium content. HDCP 2.3 is applied in transmitter, receiver, and repeater configurations. HDCP 2.3 is backwards compatible with HDCP 2.2. HDCP 1.4 is also supported to provide interoperability with legacy devices.

The ADV7672 is configured via I²C using a high level host controller interface (API).

The ADV7672 is provided in a 108-lead, lead frame chip scale package (LFCSP) with an exposed paddle and is specified over a 0°C to 70°C temperature range.

Customers that wish to sample or purchase the ADV7672 must be licensed HDMI 2.1 adopters listed at HDMI.org and licensed HDCP 2.x adopters listed at Digital-CP.com.

APPLICATIONS

• TV
• Home theater
• Industrial switching

TThe SSM3582A is a fully integrated, high efficiency, digital input stereo Class-D audio amplifier. The device can operate from a single supply and requires only a few external components, significantly reducing the circuit bill of materials.

A proprietary, spread spectrum Σ-Δ modulation scheme enables direct connection to the speaker and ensures state-of-the-art analog performance while lowering radiated emissions compared to other Class-D architectures. An optional ultralow electromagnetic interference (EMI) mode significantly reduces radiated emissions above 100 MHz, enabling longer speaker cable lengths. Audio is transmitted digitally to the amplifier, minimizing the possibility of signal corruption in digital environments. The amplifier provides outstanding analog performance, with a 106 dB signal-to-noise ratio and a low 0.004% total harmonic distortion + noise (THD + N).

The SSM3582A operates from a single 4.5 V to 16.5 V supply and is capable of delivering 2× 15 W rms continuously into 8 Ω and 4 Ω loads at <1% total harmonic distortion (THD). The efficient modulation scheme maintains excellent power efficiency over a wide range of impedances: 93.8% into an 8 Ω load and 90.6% into a 4 Ω load. Optimization of the output pulse maintains performance at impedances as low as 3 Ω/5 μH, enabling its use with extended bandwidth tweeters.

The pulse code modulation (PCM) audio serial port supports most common protocols, such as I²S, left justified, and time division multiplexing (TDM), and can address up to 16 devices on a single interface, for up to 32 audio playback channels.

IC operation is controlled through a dedicated I²C interface. The two ADDRx pins (2×, five-level) define up to 16 individual addresses in I²C and standalone modes and automatically set the default TDM slots attribution.

A micropower shutdown mode is triggered by removing the digital audio interface clock, with a typical current of <1 μA. A software power-down mode is also available.

An automatic power-down feature shuts down the amplifier and the digital-to-analog converter (DAC) when no signal is present at the input, minimizing power consumption during digital silence. The device restarts when nonzero data is present at the input. Mute and unmute transitions are pop and click free.

The SSM3582A is specified over the commercial temperature range of −40°C to +85°C. The device has built in thermal shutdown and output short-circuit protection, as well as an early thermal warning with programmable gain limiting to maintain operation.

The SSM3582A is available in a 40-lead, 6 mm × 6 mm lead frame chip scale package (LFCSP), with a thermal pad to improve heat dissipation.

Applications

• Mobile computing
• All in one computers
• Portable electronics
• Wireless speakers
• Televisions

The ADAU1462/ADAU1466 are automotive qualified audio processors that far exceed the digital signal processing capabilities of earlier SigmaDSP^® devices. They are pin and register compatible with each other, as well as with the ADAU1450/ADAU1451/ADAU1452 SigmaDSP processors. The restructured hardware architecture is optimized for efficient audio processing. The audio processing algorithms support a seamless combination of stream processing (sample by sample), multirate processing, and block processing paradigms. The SigmaStudio™ graphical programming tool enables the creation of signal processing flows that are interactive, intuitive, and powerful. The enhanced digital signal processor (DSP) core architecture enables some types of audio processing algorithms to be executed using significantly fewer instructions than were required on previous SigmaDSP generations, leading to vastly improved code efficiency.

The 1.2 V, 32-bit DSP core can run at frequencies of up to 294.912 MHz and execute up to 6144 SIMD instructions per sample at the standard sample rate of 48 kHz. Powerful clock generator hardware, including a flexible phase-locked loop (PLL) with multiple fractional integer outputs, supports all industry standard audio sample rates. Nonstandard rates over a wide range can generate up to 15 sample rates simultaneously. These clock generators, along with the on board asynchronous sample rate converters (ASRCs) and a flexible hardware audio routing matrix, make the ADAU1462/ADAU1466 ideal audio hubs that greatly simplify the design of complex multirate audio systems.

The ADAU1462/ADAU1466 interface with a wide range of analog-to-digital converters (ADCs), digital-to-analog converters (DACs), digital audio devices, amplifiers, and control circuitry with highly configurable serial ports, I²C, serial peripheral interface (SPI), Sony/Philips Digital Interconnect Format (S/PDIF) interfaces, and multipurpose input/output (I/O) pins. Dedicated decimation filters can decode the pulse code modulation (PDM) output of up to four MEMS microphones.

Independent slave and master I²C/SPI control ports allow the ADAU1462/ADAU1466 to be programmed and controlled by an external master device such as a microcontroller, and to program and control slave peripherals directly. Self boot functionality and the master control port enable complex standalone systems.

The power efficient DSP core can execute at high computational loads while consuming only a few hundred milliwatts (mW) in typical conditions. This relatively low power consumption and small footprint make the ADAU1462/ADAU1466 ideal replacements for large, general-purpose DSPs that consume more power at the same processing load.

Applications

• Automotive audio processing
  
  • Head units
  • Distributed processors
  • Rear seat entertainment systems
  • Trunk amplifiers
• Commercial and professional audio processing

The SSM3515 is a fully integrated, high efficiency, mono Class-D audio amplifier with digital inputs. The application circuit requires a minimum of external components and can operate from a single 4.5 V to 17 V supply. It can deliver 8.4 W of output power into an 8 Ω load or 15.8 W into an 4 Ω load from a 12 V power supply, or 31.3 W into an 4 Ω load from a 17 V power supply, all with 1% THD + N.

The SSM3515 features a high efficiency, low noise modulation scheme that requires no external LC output filters. This scheme provides high efficiency even at low output power. It operates with 92% efficiency at 7 W into an 8 Ω load or 88% efficiency at 15 W into 4 Ω from a 12 V supply.

Spread spectrum pulse density modulation provides lower EMI radiated emissions compared with other Class-D architectures, particularly above 100 MHz.

The digital input eliminates the need for an external digital-to-analog converter (DAC). The SSM3515 has a micropower shutdown mode with a typical shutdown current of 39 nA at the 12 V PVDD supply. The device also includes pop and click suppression circuitry that minimizes voltage glitches at the output during turn on and turn off.

The SSM3515 operates with or without an I2C control interface. The SSM3515 is specified over the commercial temperature range (−40°C to +85°C). It has built in thermal shutdown and output short-circuit protection. It is available in a halide-free, 20-ball, 1.8 mm × 2.2 mm wafer-level chip scale package (WLCSP).

APPLICATIONS

• Notebooks
• Portable electronics
• Home audio

The SSM3525 is a fully integrated, high efficiency, mono Class D audio amplifier with digital input and digitized output of output voltage, output current, and PV_DD supply. The application circuit requires few external components and can operate from 4.5 V to 17 V (PV_DD) and 1.8 V (IOV_DD) supplies. It is capable of delivering 8.3 W of continuous output power into an 8 Ω load (or 15.3 W into 4 Ω) with <1% THD + N from a 12 V supply, or 30.2 W into an 4 Ω load from a 17 V power supply, all with <1% THD + N.

The SSM3525 features a high efficiency, low noise modulation scheme that requires no external inductor/capacitor (LC) output filters. This scheme continues to provide high efficiency even at low output power. It operates with 92% efficiency at 9W into an 8 Ω load, 12V or 89% efficiency at 20 W into 4 Ω from a 17 V supply, (should now match the table)and it has an signal-to-noise ratio (SNR) of 107 dB A weighted.

Spread spectrum pulse density modulation provides lower electromagnetic interference (EMI) radiated emissions compared with other Class-D architectures, particularly above 100 MHz.

The digital input eliminates the need of an external digital-to-analog converter (DAC). The SSM3525 has a micropower shutdown mode with a typical shut¬down current of 90 nA at 12 V PV_DD supply. Individual sense blocks can be powered down to save power when sense is not needed.

The device also includes pop and click suppression circuitry that minimizes voltage glitches at the output during turn on and turn off.

Current sensing is accomplished using an integrated analog-to-digital converter (ADC) and internal sense resistor. The digitized voltage and current information can be returned in various serial audio formats, including I²S, time division multiplexing (TDM) and pulse density modulation (PDM).

The SSM3525 includes an integrated regulator to generate the required 5 V analog supply. Alternatively, if an external 5 V rail from a dc-to-dc converter is available, it can improve system efficiency.

The SSM3525 is designed to operate with an I²C control interface and specified over the temperature range −40°C to +85°C. It has built-in thermal shutdown and output short-circuit protection. It is available in a halide free, 23-ball, 2.26 mm × 2.38 mm wafer-level chip scale package (WLCSP).

Applications

• Mobile computing
• Portable electronics

Reaching speeds of up to 1 GHz, the ADSP-2156x processors are members of the SHARC^® family of products. The ADSP-2156x processor is based on the SHARC+^® single core. The ADSP-2156x SHARC processors are members of the SIMD SHARC family of digital signal processors (DSPs) that feature Analog Devices, Inc., Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with large on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). New additions to the SHARC+ core include cache enhancements and branch prediction, while maintaining instruction set compatibility to previous SHARC products.

By integrating a rich set of industry-leading system peripherals and memory (see Table 1 in the data sheet), the SHARC+ processor is the platform of choice for applications that require programmability similar to reduced instruction set computing (RISC), multimedia support, and leading edge signal processing in one integrated package. These applications span a wide array of markets, including automotive, professional audio, and industrial-based applications that require high floating-point performance.

APPLICATIONS

• Automotive:
  • audio amplifier, head unit, ANC/RNC, rear seat entertainment, digital cockpit, ADAS
• Consumer & Professional Audio:
  • speakers, sound bars, AVRs, conferencing systems, mixing consoles, microphone arrays, headphones

The EVAL-MELODY-8 board is a platform that allows users to evaluate Analog Devices, Inc., products intended for decoding high quality, digital audio signals.

The EVAL-MELODY-8 board includes a Blackfin^® ADSPBF524 processor for system control and a SHARC^® ADSP-21569, which is a SHARC+^® single core, high performance, digital signal processor for audio decoding. The evaluation board also includes the ADV7625 High-Definition Multimedia Interface (HDMI^®) transceiver with high bandwidth digital content protection (HDCP) 1.4 technology. To order the EVAL-MELODY-8 board, the user must be licensed for the HDCP 1.4 technology.

Full specifications for the ADSP-21569 are listed in the ADSP-21569 data sheet. Full specifications for the ADSP-BF524 are listed in the ADSP-BF524 data sheet. Consult the data sheets in conjunction with this user guide when using the EVAL-MELODY-8 board.

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These boards contain an integrated circuit that requires the recipient to be a licensee of HDCP technology. Please contact your local sales office for more information.