Instrumenting 5G

The AD9082 mixed signal front-end (MxFE^®) is a highly integrated device with a 16-bit, 12 GSPS maximum sample rate, RF digital-to-analog converter (DAC) core, and 12-bit, 6 GSPS maximum sample rate, RF analog-to-digital converter (ADC) cores. The AD9082 is well suited for applications requiring both wideband ADCs and DACs to process signal(s) having wide instantaneous bandwidth. The device features eight transmit lanes and eight receive lanes that support 24.75 Gbps/lane JESD204C or 15.5 Gbps/lane JESD204B standards. The device also has an on-chip clock multiplier and digital signal processing (DSP) capability targeted at either wideband or multiband, direct to RF applications. The DSP datapaths can be bypassed to allow a direct connection between the converter cores and the JESD204B/C data transceiver port. The device also features low latency loopback, frequency hopping modes, and datapath multiplexer (mux) configurations useful for phase array radar system and electronic warfare applications. Two models for the AD9082 are offered. The 4D2AC model supports four DACs and two ADCs. The 2D2AC model supports two DACs and two ADCs.

APPLICATIONS

• Wireless communications infrastructure
• Microwave point-to-point, E-band and 5G mmWave
• Broadband communications systems
• DOCSIS 3.1 and 4.0 CMTS
• Phased array radar and electronic warfare
• Electronic test and measurement systems

The AD9213 is a single, 12-bit, 6 GSPS/10.25 GSPS, radio frequency (RF) analog-to-digital converter (ADC) with a 6.5 GHz input bandwidth. The AD9213 supports high dynamic range frequency and time domain applications requiring wide instantaneous bandwidth and low conversion error rates (CER). The AD9213 features a 16-lane JESD204B interface to support maximum bandwidth capability.

The AD9213 achieves dynamic range and linearity performance while consuming <4.6 W typical. The device is based on an interleaved pipeline architecture and features a proprietary calibration and randomization technique that suppresses interleaving spurious artifacts into its noise floor. The linearity performance of the AD9213 is preserved by a combination of on-chip dithering and calibration, which results in excellent spurious-free performance over a wide range of input signal conditions. 

Applications that require less instantaneous bandwidth can benefit from the on-chip, digital signal processing (DSP) capability of the AD9213 that reduces the output data rate along with the number of JESD204B lanes required to support the device. The DSP path includes a digital downconverter (DDC) with a 48-bit, numerically controlled oscillator (NCO), followed by an I/Q digital decimator stage that allows selectable decimation rates that are factors of two or three. For fast frequency hopping applications, the AD9213 NCO supports up to 16 profile settings with a separate trigger input, allowing wide surveillance frequency coverage at a reduced JESD204B lane count.

The AD9213 supports sample accurate multichip synchronization that includes synchronization of the NCOs. The AD9213 is offered in a 192-ball ball grid array (BGA) package and is specified over a junction temperature range of −20°C to +115°C.

The AD9209 is a quad, 12-bit, 4 GSPS analog-to-digital converter (ADC). The ADC input features an on-chip wideband buffer with overload protection. This device is designed to support applications capable of direct sampling wideband signals up to 8 GHz. An on-chip, low phase noise, phase-locked loop (PLL) clock synthesizer is available to generate the ADC sampling clock, simplifying the printed circuit board (PCB) distribution of a high frequency clock signal. A clock output buffer is available to transmit the ADC sampling clock to other devices.

The quad ADC cores have code error rates (CER) better than 1 × 10−20. Low latency fast detection and signal monitoring are available for automatic gain control (AGC) purposes. A flexible 192-tap programmable finite impulse response filter (PFIR) is avail-able for digital filtering and/or equalization. Programmable integer and fractional delay blocks support compensation for analog delay mismatches.

The digital signal processing (DSP) block consisting of two coarse digital down converters (DDCs) and four fine DDCs per pair of ADCs. Each ADC can operate with one or two main DDC stages in support of multiband applications. The four additional fine DDC stages are available to support up to four bands per ADC The 48-bit numerically controlled oscillators (NCOs) associated with each DDC support fast frequency hopping (FFH) while maintaining synchronization with up to 16 unique frequency assignments selected via the general-purpose input and output (GPIOx) pins or the serial port interface (SPI).

The AD9209 supports one or two JTx links that can be configured for either JESD204B or JESD204C subclass operation, thus allowing for different datapath configurations for each ADC. Multidevice synchronization is supported through the SYSREF± input pins.

APPLICATIONS

• Wireless communications infrastructure
• Microwave point-to-point, E-band, and 5G mm wave
• Broadband communications systems
• DOCSIS 3.1 and 4.0 CMTS
• Phased array radar and electronic warfare
• Electronic test and measurement systems

The ADF4372 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter and an external reference frequency. The wideband microwave voltage controlled oscillator (VCO) design allows frequencies from 62.5 MHz to 16 GHz to be generated.

The ADF4372 has an integrated VCO with a fundamental output frequency ranging from 4000 MHz to 8000 MHz. In addition, the VCO frequency is connected to a divide by 1, 2, 4, 8, 16, 32, or 64 circuit that allows the user to generate radio frequency (RF) output frequencies as low as 62.5 MHz at RF8x. A frequency multiplier at RF16x generates from 8 GHz to 16 GHz. RFAUX8x duplicates the frequency range of RF8x or permits direct access to the VCO output. To suppress the unwanted products of frequency multiplication, a harmonic filter exists between the multiplier and the output stage of RF16x.

Control of all on-chip registers is through a 3-wire interface. The ADF4372 operates with analog and digital power supplies ranging from 3.15 V to 3.45 V, and 5 V for the VCO power supply. The ADF4372 also contains hardware and software power-down modes.

APPLICATIONS

• Wireless infrastructure (multicarrier global system for mobile communication (MC-GSM), 5 G)
• Test equipment and instrumentation
• Clock generation
• Aerospace and defense

The ADF4401A is a fully integrated, system in package (SiP) translation loop (also known as an offset loop) module that includes a voltage controlled oscillator (VCO) and calibration phase-locked loop (PLL) circuit. Designed for highly jitter sensitive applications, this solution reduces board space and complexity compared to traditional discrete translation loop solutions designed on a printed circuit board (PCB). The time to market is significantly reduced by taking advantage of this highly integrated solution with in package circuitry and enhanced isolation that attenuates spurious components. The ADF4401A provides a frequency synthesis solution for engineers designing highly competitive systems.

The ADF4401A requires an external phase detector or phase frequency detector (PFD) and an external local oscillator (LO) to form a frequency synthesis solution.

The ADF4401A implements an integrated downconversion mixing stage in the feedback loop that sets the loop gain to 1 and minimizes the in band phase noise. By combining the frequency downconversion stage and low noise, integrated, wideband, VCO technology from Analog Devices, Inc., the ADF4401A offers a wideband jitter performance of 9 fs rms at 8 GHz output. The output jitter performance is largely dependent on the performance of the external offset LO.

The ADF4401A module uses an internal PFD and VCO calibration circuitry to select the appropriate VCO band. The user can disable the calibration circuitry and close the loop using the external PFD. All on-chip registers are controlled via a serial port interface (SPI).

APPLICATIONS

• Instrumentation and measurement
• Automated test equipment
• Aerospace and defense

The ADMV1013 is a wideband, microwave upconverter optimized for point to point microwave radio designs operating in the 24 GHz to 44 GHz radio frequency (RF) range.

The upconverter offers two modes of frequency translation. The device is capable of direct conversion to RF from baseband in-phase quadrature (I/Q) input signals, as well as single-sideband (SSB) upconversion from complex intermediate frequency (IF) inputs. The baseband I/Q input path can be disabled and modulated complex IF signals, anywhere from 0.8 GHz to 6.0 GHz, can be inserted in the IF path and upconverted to 24 GHz to 44 GHz while suppressing the unwanted sideband by typically better than 26 dBc. The serial port interface (SPI) allows adjustment of the quadrature phase and mixer gate voltage to allow optimum sideband suppression and local oscillator (LO) nulling. In addition, the SPI interface allows powering down the output envelope detector to reduce power consumption.

The ADMV1013 upconverter comes in a 40-terminal land grid array package (LGA) package. The ADMV1013 operates over the −40°C to +85°C case temperature range.

Applications

• Point to point microwave radios
• Radar, electronic warfare systems
• Instrumentation, automatic test equipment (ATE)

The ADMV1014 is a silicon germanium (SiGe), wideband, microwave downconverter optimized for point to point microwave radio designs operating in the 24 GHz to 44 GHz frequency range.

The downconverter offers two modes of frequency translation. The device is capable of direct quadrature demodulation to baseband inphase (I)/quadrature (Q) output signals, as well as image rejection downconversion to a complex intermediate frequency (IF) output carrier frequency. The baseband outputs can be dc-coupled, or, more typically, the I/Q outputs are ac-coupled with a sufficiently low high-pass corner frequency to ensure adequate demodulation accuracy. The serial port interface (SPI) allows fine adjustment of the quadrature phase to allow the user to optimize I/Q demodulation performance. Alternatively, the baseband I/Q outputs can be disabled, and the I/Q signals can be passed through an on-chip active balun to provide two single-ended complex IF outputs anywhere between 800 MHz and 6000 MHz. When used as an image rejecting downconverter, the unwanted image term is typically suppressed to better than 30 dBc below the wanted sideband. The ADMV1014 offers a flexible local oscillator (LO) system, including a frequency quadruple option allowing up to a 41 GHz range of LO input frequencies to cover a radio frequency (RF) input range as wide as 24 GHz to 44 GHz. A square law power detector is provided to allow monitoring of the power levels at the mixer inputs. The detector output provides closed-loop control of the RF input variable attenuator through an external op amp error integrator circuit option.

The ADMV1014 downconverter comes in a compact, thermally enhanced, 5 mm × 5 mm LGA package. The ADMV1014 operates over the −40°C to +85°C case temperature range.

Applications

• Point to point microwave radios
• Radar, electronic warfare systems
• Instrumentation, automatic test equipment (ATE)

The ADRF5043 is a nonreflective, SP4T switch manufactured in the silicon on insulator (SOI) process.

The ADRF5043 operates from 9 kHz to 44 GHz with an insertion loss of lower than 2.5 dB and an isolation of higher than 36 dB. The device has a RF input power handling capability of 24 dBm for both through and terminated paths.

The ADRF5043 requires a dual-supply voltage of +3.3 V and −3.3 V. The device employs CMOS- and low voltage transistor to transistor logic (LVTTL)-compatible controls.

The ADRF5043 has enable and logic select controls to feature all off state and port mirroring, respectively.

The ADRF5043 is pin compatible with the ADRF5042 fast switching version, which operates from 100 MHz to 44 GHz.

The ADRF5043 comes in a 24-terminal, 3 mm × 3 mm, RoHS compliant, land grid array (LGA) package and can operate from −40°C to +105°C.

Applications

• Industrial Scanners
• Test instrumentation
• Cellular infrastructure—millimeterwave (mmWave) 5G
• Military radios, radars, electronic counter measures (ECMs)
• Microwave radios and very small aperture terminals (VSATs)

The HMC8411LP2FE is a gallium arsenide (GaAs), monolithic microwave integrated circuit (MMIC), pseudomorphic high electron mobility transistor (pHEMT), low noise wideband amplifier that operates from 0.01 GHz to 10 GHz.

The HMC8411LP2FE provides a typical gain of 15.5 dB, a 1.7 dB typical noise figure, and a typical output third-order intercept (OIP3) of 34 dBm, requiring only 55 mA from a 5 V supply voltage. The saturated output power (P_SAT) of 19.5 dBm typical enables the low noise amplifier (LNA) to function as a local oscillator (LO) driver for many of Analog Devices, Inc., balanced, in-phase/quadrature (I/Q), or image rejection mixers.

The HMC8411LP2FE also features inputs and outputs that are internally matched to 50 Ω, making the device ideal for surface-mounted technology (SMT)-based, high capacity microwave radio applications.

The HMC8411LP2FE is housed in a RoHS-compliant, 2 mm × 2 mm, 6-lead LFCSP.

Multifunction pin names may be referenced by their relevant function only.

Applications

• Test instrumentation
• Military communications

The LT3042 is a high performance low dropout linear regulator featuring LTC’s ultralow noise and ultrahigh PSRR architecture for powering noise sensitive RF applications. Designed as a precision current reference followed by a high performance voltage buffer, the LT3042 can be easily paralleled to further reduce noise, increase output current and spread heat on the PCB.

The device supplies 200mA at a typical 350mV dropout voltage. Operating quiescent current is nominally 2mA and drops to <<1μA in shutdown. The LT3042’s wide output voltage range (0V to 15V) while maintaining unity-gain operation provides virtually constant output noise, PSRR, bandwidth and load regulation, independent of the programmed output voltage. Additionally, the regulator features programmable current limit, fast start-up capability and programmable power good to indicate output voltage regulation.

The LT3042 is stable with a minimum 4.7μF ceramic output capacitor. Built-in protection includes reverse battery protection, reverse current protection, internal current limit with foldback and thermal limit with hysteresis. The LT3042 is available in thermally enhanced 10-Lead MSOP and 3mm × 3mm DFN packages.

Applications

• RF Power Supplies: PLLs, VCOs, Mixers, LNAs
• Very Low Noise Instrumentation
• High Speed/High Precision Data Converters
• Medical Applications: Imaging, Diagnostics
• Precision Power Supplies
• Post-Regulator for Switching Supplies