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The Automotive Audio Bus (A²B^®) provides a multichannel, I²S/TDM link over distances of up to 15 m between nodes. It embeds bidirectional synchronous pulse-code modulation (PCM) data (for example, digital audio), clock, and synchronization signals onto a single differential wire pair. A²B supports a direct point to point connection and allows multiple, daisy-chained nodes at different locations to contribute and/or consume time division multiplexed (TDM) channel content.

A²B is a single-master, multiple-slave system where the transceiver at the host controller is the master. The master generates clock, synchronization, and framing for all slave nodes. The master A²B transceiver is programmable over a control port (I²C) for configuration and read back. An extension of this control port is embedded in the A²B data stream, which grants direct access of registers and status information on slave transceivers as well as I²C to I²C communication over distance.

The transceiver can connect directly to general-purpose digital signal processors (DSPs), field-programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), microphones, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and codecs through a multichannel I²S/TDM interface. It also provides a pulse density modulation (PDM) interface for direct connection of up to four PDM digital microphones.

Finally, the transceiver also supports an A²B bus powering feature, where the master node supplies voltage and current to the slave nodes over the same daisy-chained, twisted pair wire cable as used for the communication link.

¹ N/A means not applicable.
² PDM microphones must be connected to the DRX0/IO5 pin.

Applications

• Audio communication link
• Microphone arrays
  
  • Beamforming
  • Hands free and in car communication
• Active and road noise cancellation
• Audio/video conferencing systems

The Automotive Audio Bus (A²B^®) provides a multichannel, I²S/TDM link over distances of up to 15 m between nodes. It embeds bidirectional synchronous pulse-code modulation (PCM) data (for example, digital audio), clock, and synchronization signals onto a single differential wire pair. A²B supports a direct point to point connection and allows multiple, daisy-chained nodes at different locations to contribute and/or consume time division multiplexed (TDM) channel content.

A²B is a single-master, multiple-slave system where the transceiver at the host controller is the master. The master generates clock, synchronization, and framing for all slave nodes. The master A²B transceiver is programmable over a control port (I²C) for configuration and read back. An extension of this control port is embedded in the A²B data stream, which grants direct access of registers and status information on slave transceivers as well as I²C to I²C communication over distance.

The transceiver can connect directly to general-purpose digital signal processors (DSPs), field-programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), microphones, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and codecs through a multichannel I²S/TDM interface. It also provides a pulse density modulation (PDM) interface for direct connection of up to four PDM digital microphones.

Finally, the transceiver also supports an A²B bus powering feature, where the master node supplies voltage and current to the slave nodes over the same daisy-chained, twisted pair wire cable as used for the communication link.

¹ N/A means not applicable.
² PDM microphones must be connected to the DRX0/IO5 pin.

Applications

• Audio communication link
• Microphone arrays
  
  • Beamforming
  • Hands free and in car communication
• Active and road noise cancellation
• Audio/video conferencing systems

The Automotive Audio Bus (A²B^®) provides a multichannel, I²S/TDM link over distances of up to 15 m between nodes. It embeds bidirectional synchronous pulse-code modulation (PCM) data (for example, digital audio), clock, and synchronization signals onto a single differential wire pair. A²B supports a direct point to point connection and allows multiple, daisy-chained nodes at different locations to contribute and/or consume time division multiplexed (TDM) channel content.

A²B is a single-master, multiple-slave system where the transceiver at the host controller is the master. The master generates clock, synchronization, and framing for all slave nodes. The master A²B transceiver is programmable over a control port (I²C) for configuration and read back. An extension of this control port is embedded in the A²B data stream, which grants direct access of registers and status information on slave transceivers as well as I²C to I²C communication over distance.

The transceiver can connect directly to general-purpose digital signal processors (DSPs), field-programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), microphones, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and codecs through a multichannel I²S/TDM interface. It also provides a pulse density modulation (PDM) interface for direct connection of up to four PDM digital microphones.

Finally, the transceiver also supports an A²B bus powering feature, where the master node supplies voltage and current to the slave nodes over the same daisy-chained, twisted pair wire cable as used for the communication link.

¹ N/A means not applicable.
² PDM microphones must be connected to the DRX0/IO5 pin.

Applications

• Audio communication link
• Microphone arrays
  
  • Beamforming
  • Hands free and in car communication
• Active and road noise cancellation
• Audio/video conferencing systems

The ADSP-SC57x/ADSP-2157x processors are members of the SHARC^® family of products. The ADSP-SC57x processor is based on the SHARC+^® dual-core and the arm^® Cortex^®-A5 core. The ADSP-SC57x/ADSP-2157x SHARC processors are members of the single-instruction, multiple data (SIMD) SHARC family of digital signal processors (DSPs) that feature Analog Devices Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with large on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). New additions to the SHARC+ core include cache enhancements and branch prediction, while maintaining instruction set compatibility to previous SHARC products.

By integrating a set of industry leading system peripherals and memory, the arm^® Cortex-A5 and SHARC processor is the platform of choice for applications that require programmability similar to reduced instruction set computing (RISC), multimedia support, and leading edge signal processing in one integrated package. These applications span a wide array of markets, including automotive, professional audio, and industrial-based applications that require high floating-point performance.

The ADAU1462/ADAU1466 are automotive qualified audio processors that far exceed the digital signal processing capabilities of earlier SigmaDSP^® devices. They are pin and register compatible with each other, as well as with the ADAU1450/ADAU1451/ADAU1452 SigmaDSP processors. The restructured hardware architecture is optimized for efficient audio processing. The audio processing algorithms support a seamless combination of stream processing (sample by sample), multirate processing, and block processing paradigms. The SigmaStudio™ graphical programming tool enables the creation of signal processing flows that are interactive, intuitive, and powerful. The enhanced digital signal processor (DSP) core architecture enables some types of audio processing algorithms to be executed using significantly fewer instructions than were required on previous SigmaDSP generations, leading to vastly improved code efficiency.

The 1.2 V, 32-bit DSP core can run at frequencies of up to 294.912 MHz and execute up to 6144 SIMD instructions per sample at the standard sample rate of 48 kHz. Powerful clock generator hardware, including a flexible phase-locked loop (PLL) with multiple fractional integer outputs, supports all industry standard audio sample rates. Nonstandard rates over a wide range can generate up to 15 sample rates simultaneously. These clock generators, along with the on board asynchronous sample rate converters (ASRCs) and a flexible hardware audio routing matrix, make the ADAU1462/ADAU1466 ideal audio hubs that greatly simplify the design of complex multirate audio systems.

The ADAU1462/ADAU1466 interface with a wide range of analog-to-digital converters (ADCs), digital-to-analog converters (DACs), digital audio devices, amplifiers, and control circuitry with highly configurable serial ports, I2C, serial peripheral interface (SPI), Sony/Philips Digital Interconnect Format (S/PDIF) interfaces, and multipurpose input/output (I/O) pins. Dedicated decimation filters can decode the pulse code modulation (PDM) output of up to four MEMS microphones.

Independent slave and master I²C/SPI control ports allow the ADAU1462/ADAU1466 to be programmed and controlled by an external master device such as a microcontroller, and to program and control slave peripherals directly. Self boot functionality and the master control port enable complex standalone systems.

The power efficient DSP core can execute at high computational loads while consuming only a few hundred milliwatts (mW) in typical conditions. This relatively low power consumption and small footprint make the ADAU1462/ADAU1466 ideal replacements for large, general-purpose DSPs that consume more power at the same processing load.

Applications

• Automotive audio processing
  
  • Head units
  • Distributed amplifiers
  • Rear seat entertainment systems
  • Trunk amplifiers
• Commercial and professional audio processing

The ADSP-SC584 processor is part of the new, high-performance, power-efficient, real-time series that delivers greater than 24 giga-floating-point operations per second using two enhanced SHARC+^® cores and advanced DSP accelerators (FFT, FIR, IIR). The ADSP-SC58x and ADSP-2158x series consume less than 2 watts, making the new processor line-up more than 5x more power efficient than previous SHARC products. This advantage provides industry leading digital signal processing performance for applications where thermal management sets the limit for power consumption, or where the higher costs and lower reliability of fans cannot be tolerated. Applications include automotive, consumer and professional audio, multi-axis motor control, and energy distribution systems.

The ADSP-SC58x products complement the SHARC+ cores and DSP accelerators with the addition of an Arm^® Cortex-A5 processor, with FPU and Neon^® DSP extensions to handle additional real-time processing tasks and manage peripherals used to interface to time-critical data in audio, industrial closed-loop control, and industrial sensing applications. These interfaces includes Gigabit Ethernet, USB High-Speed and a rich variety of other connectivity options for a flexible and simplified system design.

The ADSP-2158x family is designed for applications where a DSP co-processor is exclusively needed and includes two SHARC+ cores and a peripheral set matched to a DSP core.

The new, code-compatible, enhanced SHARC+ core features clock-rate and power-efficiency improvements and adds instruction/data cache options, native double-precision floating-point support, and a number of other new instructions. Designed for low-power and using a low-leakage CMOS process, the ADSP-SC58x/2158x families deliver 500 MHz with 105°C environments in mind and provide a roadmap to future implementations at higher performance. More than 1.8 Mbytes of fast on-chip SRAM and a DDR3/2/LP interface aid efficient real-time performance while the memory subsystem includes major enhancements with advanced DMA engines for simultaneous data transfer.

With software IP protection a growing industry security concern, Arm^® TrustZone^® security and an onboard crypto hardware accelerators are included. For applications where reliability is a critical requirement, memory parity and error-correction hardware provide higher data integrity. The overall integration and low-power features offered by the new ADSP-SC58x and ADSP-2158x series deliver significant BOM and board area savings and provide lower design complexity and reduced time to market for today’s complex applications.

The ADSP-SC58x/2158x  is supported by ADI’s award winning Crosscore^® Embedded Studio development tool suite, providing design engineers with interactive, real-time development tools that help optimize their design and speed time to market.

Analog Devices also provides the Linux Add-In for CrossCore Embedded Studio, a custom Linux board support package based on Buildroot, enabling customers interested in taking advantage of the communication stacks and application packages available for embedded Linux, running on the Arm Cortex-A5 core. Target Linux availability is September 2015 and to request, please complete the software request form and specify "Linux SC58x Support" in the Additional Comments field.

The ADSP-SC584 EZ-KIT-Lite development board and ICE-1000/2000 emulators facilitate the creation, test, and debug of advanced applications. Working in tandem with CrossCore Embedded Studio, the emulators provide state-of-the-art support for all JTAG-compliant Analog Devices processors now utilizing CoreSight^™ from Arm.

The ADSP-21584 processor is part of the new, high-performance, power-efficient, real-time series that delivers greater than 24 giga-floating-point operations per second using two enhanced SHARC+^® cores and advanced DSP accelerators (FFT, FIR, IIR). The ADSP-SC58x and ADSP-2158x series consume less than 2 watts, making the new processor line-up more than 5x more power efficient than previous SHARC products. This advantage provides industry leading digital signal processing performance for applications where thermal management sets the limit for power consumption, or where the higher costs and lower reliability of fans cannot be tolerated.  Applications include automotive, consumer and professional audio, multi-axis motor control, and energy distribution systems.

The ADSP-2158x family is designed for applications where a DSP co-processor is exclusively needed and includes two SHARC+ cores and a peripheral set matched to a DSP core.  

The new, code-compatible, enhanced SHARC+ core features clock-rate and power-efficiency improvements and adds instruction/data cache options, native double-precision floating-point support, and a number of other new instructions. Designed for low-power and using a low-leakage CMOS process, the ADSP-SC58x/2158x families deliver 500 MHz with 105°C environments in mind and provide a roadmap to future implementations at higher performance. More than 1.5 Mbytes of fast on-chip SRAM and a DDR3/2/LP interface aid efficient real-time performance while the memory subsystem includes major enhancements with advanced DMA engines for simultaneous data transfer.

With software IP protection a growing industry security concern, ARM^® TrustZone^® security and an onboard crypto hardware accelerators are included. For applications where reliability is a critical requirement, memory parity and error-correction hardware provide higher data integrity. The overall integration and low-power features offered by the new ADSP-SC58x and ADSP-2158x series deliver significant BOM and board area savings and provide lower design complexity and reduced time to market for today’s complex applications.

The ADSP-SC58x/2158x  is supported by ADI’s award winning Crosscore^®  Embedded Studio development tool suite, providing design engineers with interactive, real-time development tools that help optimize their design and speed time to market.

Additionally, ADI and Micrium have collaborated to offer µC/OS-II^® & µC/OS-III^® real-time kernels on SHARC+.

The compatible ADSP-SC584 EZ-KIT-Lite development board and ICE-1000/2000 emulators facilitate the creation, test, and debug of advanced applications. Working in tandem with CrossCore Embedded Studio, the emulators provide state-of-the-art support for all JTAG-compliant Analog Devices processors now utilizing CoreSight^™ from ARM.

The ADSP-SC57x/ADSP-2157x processors are members of the SHARC^® family of products. The ADSP-SC57x processor is based on the SHARC+^® dual-core and the arm^® Cortex^®-A5 core. The ADSP-SC57x/ADSP-2157x SHARC processors are members of the single-instruction, multiple data (SIMD) SHARC family of digital signal processors (DSPs) that feature Analog Devices Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with large on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). New additions to the SHARC+ core include cache enhancements and branch prediction, while maintaining instruction set compatibility to previous SHARC products.

By integrating a set of industry leading system peripherals and memory, the arm^® Cortex-A5 and SHARC processor is the platform of choice for applications that require programmability similar to reduced instruction set computing (RISC), multimedia support, and leading edge signal processing in one integrated package. These applications span a wide array of markets, including automotive, professional audio, and industrial-based applications that require high floating-point performance.

The SigmaStudio^® graphical development tool is the programming, development, and tuning software for the SigmaDSP^® and SHARC^® audio processors and A²B^® transceivers. Familiar audio processing blocks can be wired together as in a schematic, and the compiler generates DSP-ready code and a control surface for setting and tuning parameters. This tool allows engineers with no DSP code writing experience to easily implement a DSP into their design and yet is still powerful enough to satisfy the demands of experienced DSP designers. SigmaStudio links with both Analog Devices evaluation boards and production designs to provide full in-circuit real-time IC control.

SigmaStudio includes an extensive library of algorithms to perform audio processing such as filtering, mixing, and dynamics processing, as well as basic low-level DSP functions and control blocks. Advanced record-side processing algorithms such as Enhanced Stereo Capture and wind noise detection are included in the standard libraries. Plug-in algorithms from Analog Devices and 3rd party partners can be added to SigmaStudio's drag-and-drop library.

Along with its graphical DSP signal flow development, SigmaStudio also includes other features to speed up the design cycle from product concept to release. SigmaStudio includes tools for intuitively setting control registers, calculating tables of filter coefficients, visualizing filter magnitude and phase responses, generating C header files, and sequencing a series of controls to ease your transition from SigmaStudio to system implementation on your microcontroller.