Unified Communications and ProAV

The ADRV9002 is a highly integrated RF transceiver that has dual-channel transmitters, dual-channel receivers, integrated synthesizers, and digital signal processing functions.

The ADRV9002 is a high performance, highly linear, high dynamic range transceiver designed for performance vs. power consumption system optimization. The device is configurable and ideally suited to demanding, low power, portable and battery powered equipment. The ADRV9002 operates from 30 MHz to 6000 MHz and covers the UHF, VHF, industrial, scientific, and medical (ISM) bands, and cellular frequency bands in narrow-band (kHz) and wideband operation up to 40 MHz. The ADRV9002 is capable of both TDD and FDD operation.

The transceiver consists of direct conversion signal paths with state-of-the-art noise figure and linearity. Each complete receiver and transmitter subsystem includes dc offset correction, quadrature error correction (QEC), and programmable digital filters, which eliminate the need for these functions in the digital baseband. In addition, several auxiliary functions, such as auxiliary analog-to-digital converters (ADCs), auxiliary digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs), are integrated to provide additional monitoring and control capability.

The fully integrated phase-locked loops (PLLs) provide high performance, low power, fractional-N frequency synthesis for the transmitter, receiver, and clock sections. Careful design and layout techniques provide the isolation required in high performance personal radio applications.

All voltage controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count. The local oscillators (LOs) have flexible configuration options and include fast lock modes.

The transceiver includes low power sleep and monitor modes to save power and extend the battery life of portable devices while monitoring communications.

The fully integrated, low power digital predistortion (DPD) is optimized for both narrow-band and wideband signals and enables linearization of high efficiency power amplifiers.

The ADRV9002 core can be powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard 4-wire serial port. Other voltage supplies are used to provide proper digital interface levels and to optimize the receiver, transmitter, and auxiliary converter performance.

High data rate and low data rate interfaces are supported using configurable CMOS or low voltage differential signaling (LVDS) serial synchronous interface (SSI) choice.

The ADRV9002 is packaged in a 12 mm × 12 mm, 196-ball chip scale package ball grid array (CSP_BGA).

APPLICATIONS

• Mission critical communications
• Very high frequency (VHF), ultrahigh frequency (UHF), and cellular to 6 GHz
• Time division duplexing (TDD) and frequency division duplexing (FDD) applications

The ADV7672 is a High-Definition Multimedia Interface (HDMI^®) transceiver with crosspoint matrix switch, video mirror, video split, and video merge capabilities.

The ADV7672 supports 40 Gbps fixed rate link (FRL) and 18 Gbps transition minimized differential signaling (TMDS) video rates and provides two independent HDMI receiver ports, two independent HDMI transmitter ports, two audio ports, and an enhanced audio return channel (eARC) interface.

Each HDMI receiver and transmitter supports 8k30 RGB/YCbCr 4:4:4 10-bit video, 8k60 YCbCr 4:2:0 10-bit high definition video, and 4k120 4:4:4 10-bit high frame rate video.

Each audio port can be independently configured as either an audio extraction or audio insertion port. The audio ports support 8-channel, 192 kHz, 24-bit pulse coded modulation (PCM) and compressed audio formats including high bitrate formats.

The eARC interface can be configured as either an eARC transmitter or an eARC receiver. The eARC interface supports 8-channel 192 kHz PCM audio and high bit rate audio (HBR) compressed audio formats including Dolby TrueHD^™ and DTS-HD^™. Audio return channel (ARC) is also supported on the eARC interface.

The ADV7672 supports display stream compression (DSC) 1.2a data passthrough and high dynamic range (HDR) metadata passthrough for HDMI dynamic HDR, HDR10+, and Dolby Vision^™.

The ADV7672 implements the High-bandwidth Digital Content Protection (HDCP) 2.3 specification to protect the delivery of premium content. HDCP 2.3 is applied in transmitter, receiver, and repeater configurations. HDCP 2.3 is backwards compatible with HDCP 2.2. HDCP 1.4 is also supported to provide interoperability with legacy devices.

The ADV7672 is configured via I²C using a high level host controller interface (API).

The ADV7672 is provided in a 108-lead, lead frame chip scale package (LFCSP) with an exposed paddle and is specified over a 0°C to 70°C temperature range.

Customers that wish to sample or purchase the ADV7672 must be licensed HDMI 2.1 adopters listed at HDMI.org and licensed HDCP 2.x adopters listed at Digital-CP.com.

APPLICATIONS

• TV
• Home theater
• Industrial switching

The ADAU1787 is a codec with four inputs and two outputs that incorporates two digital signal processors (DSPs). The path from the analog input to the DSP core to the analog output is optimized for low latency and is ideal for noise cancelling headsets. With the addition of just a few passive components, the ADAU1787 provides a complete headset solution.

Note that throughout the data sheet, multifunction pins, such as BCLK_0/MP1, are referred to either by the entire pin name or by a single function of the pin, for example, BCLK_0, when only that function is relevant.

Applications

• Noise cancelling handsets, headsets, and headphones
• Bluetooth ANC handsets, headsets, and headphones
• Personal navigation devices
• Digital still and video cameras
• Musical instrument effect processors
• Multimedia speaker systems
• Smartphones

The ADAU1472 is a high quality SigmaDSP^® digital audio processor with a large internal memory, enabling efficient audio source separation, far field voice capture, speech processing, deep learning, and advanced audio signal processing. The processor combines the highly optimized Cadence^® Tensilica^® HiFi^® 4 audio/voice processor with custom Analog Devices, Inc., instruction extensions for math acceleration, and a flexible input and output architecture. The HiFi 4 processor supports four 32-bit × 32-bit multiplier accumulators (MACs) per cycle with 72-bit accumulators, dual 64-bit memory load, and a native Institute of Electrical and Electronics Engineers (IEEE) single precision, floating-point multiplier.

The ADAU1472 processor offers performance up to 270.336 MHz, supports low latency, sample by sample audio processing, and block by block processing paradigms in parallel. The integer phase-locked loop (PLL) and flexible clock generator hardware can generate up to 15 audio sample rates simultaneously (8 kHz to 192 kHz). These clock generators, along with the on-board asynchronous sample rate converters (ASRCs) and flexible hardware audio routing matrix, greatly simplify the design of complex audio systems.

The HiFi 4 digital signal processor (DSP) core has 480 kB of L1 memory running at the DSP core clock rate, which consists of 256 kB data random access memory (RAM), 64 kB instruction RAM, 128 kB data cache, and 32 kB instruction cache, along with 2 MB of L2 system static random access memory (SRAM) running at one half of the DSP core clock rate. The processor also supports up to 2 GB of external flash memory to enable the storage of large data tables and self boot code.

Dual on-chip power domains allow low power operation, including the capability of routing audio through a flexible audio routing matrix with IOVDD as the only active supply. The configurable voice detection hardware can detect human speech onset while operating in a low power state and can generate both internal DSP and external wake-up signals.

The ADAU1472 interfaces with a wide range of analog-to-digital converters (ADCs), digital-to-analog converters (DACs), digital audio devices, amplifiers, and control circuitry due to its highly configurable serial ports, Sony/Philips digital interface format (S/PDIF) interfaces, and multipurpose input/output pins. The device can also directly interface with up to 14 pulse density modulated (PDM) output microphones due to integrated decimation filters specifically designed for that purpose. The PDM outputs with integrated interpolation filters provide direct connectivity to PDM input Class D amplifiers.

The processor has two serial peripheral interface (SPI) bus master control ports that allow the device to communicate with multiple SPI-compatible devices including support for single, dual, and quad input/output operation. In addition, the SPI flash port allows direct memory mapped read access with minimal central processing unit (CPU) overhead and standalone self boot operation.

The combined high performance DSP core, large RAM, and small footprint make the ADAU1472 an ideal replacement for large, general-purpose DSPs that consume more power for the same processing load.

Applications

• Far field voice interface devices
• Audio source separation
• Embedded deep learning for audio
• Commercial and professional audio processing