Wireless Infrastructure

This circuit is a high performance, dual channel IF sampling receiver, also called a “main” and "diversity" receiver in base station terminology. The downconverting receiver uses a single IF frequency of 153.6 MHz and includes a dual downconverting mixer, digitally controlled dual VGA, dual ADC, and clock synthesizer. The circuit takes an incoming RF waveform and outputs a dual 14-bit resolution digital data stream. It is optimized for high frequency IF sampling and provides exceptional spurious-free dynamic range (SFDR) performance of 79.61 dBc with a sampling rate of 122.88 MSPS at the high gain setting.

This circuit is a complete implementation of a low noise microwave fractional-N PLL using the ADF4156 as the core fractional-N PLL device. The ADF5001 external prescaler is used to extend the frequency range of the PLL up to 18 GHz. An ultralow noise OP184 op amp with appropriate biasing and filtering is used to drive a microwave VCO to implement a complete low noise PLL at 12 GHz with a measured integrated phase noise of 0.35 ps rms. This function is typically used to generate the local oscillator frequency (LO) for applications such as microwave point-to-point systems, test and measurement equipment, automotive radar, and military applications.

The circuit shown in Figure 1 generates a high voltage signal that controls the capacitance of a BST (barium strontium titanate) capacitor. The capacitance of a BST capacitor can be altered by applying a voltage of between 0 V and 30 V to the correct terminal. This changes the thickness of the dielectric and, hence, the capacitance. BSTs are often used for tuning antenna arrays or tunable filters. Clearly, there is an advantage in being able to tune these applications—for example, compensating for component tolerance errors, fine tuning the cutoff frequency of a filter, or network impedance matching for tunable antennas.

This application requires a convenient, compact, and low cost circuit to generate the high voltage power supply because it is often not practical to add a separate supply simply for this function alone. The circuit in Figure 1 meets these requirements using the ADP1613 boost converter and the AD5504 30 V/60 V DAC. Total board area for the boost regulator circuit is only 43 mm². The ADP1613 is available in an 8-lead MSOP package and the AD5504 in a 16-lead TSSOP.

The standard single channel direct digital synthesizer (DDS) does not switch between frequencies in a phase coherent manner. By design, DDS frequency transitions are phase continuous (see Figure 2, for example). However, the circuit shown in Figure 1 demonstrates how to configure the AD9958/AD9959 multichannel DDS for a robust phase coherent FSK (frequency shift keying) modulator by summing the outputs of the multichannel DDS together.

A multichannel DDS virtually eliminates temperature and timing issues between channels compared to synchronizing multiple single channel devices for the same application. For instance, multichannel DDS outputs, though independent, share the same system clock edges in the chip. Consequently, the system clock edges across multiple chips would not track as well over temperature and power supply deviations compared to an integrated multichannel DDS. As a result, a multichannel DDS is better suited for producing a closer to ideal phase coherent frequency transition at the summed output.

This circuit uses the ADL5902 TruPwr^™ detector to measure the rms signal strength of RF signals with varying crest factors (peak-to-average ratio) over a dynamic range of approximately 65 dB and operates at frequencies from 50 MHz up to 9 GHz.

The measurement result is provided as serial data at the output of a 12-bit ADC (AD7466). A simple 4-point system calibration at ambient temperature is performed in the digital domain.

The interface between the RF detector and the ADC is straightforward, consisting of two signal scaling resistors and no active components. In addition, the ADL5902 internal 2.3 V reference voltage provides the supply and reference voltage for the micropower ADC. The AD7466 has no pipeline delay and is operated as a read-only SAR ADC.

The overall circuit achieves temperature stability of approximately ±0.5 dB.

Data is shown for the two devices operating over a −40°C to +85°C temperature range.

The circuit shown in Figure 1 uses the ADL5535/ADL5536 single-ended IF low noise 50 Ω gain block to drive the AD9268 16-bit differential input analog-to-digital converter (ADC). The circuit includes an interstage bandpass filter for noise reduction and anti-aliasing. The use of a single-ended IF gain stage followed by a transformer to perform the single-ended-to-differential conversion is an optimum solution for this application where both low noise and low distortion are required.

The ADL5535/ADL5536 is a high linearity (third order output intercept, OIP3 = +45 dBm at 190 MHz), single-ended, fixed gain amplifier that can be used as a driver for high performance IF sampling of analog-to-digital converters. The ADL5535 has a gain of 16 dB and provides a simple approach to raise the signal from approximately 400 mV p-p to the 2 V p-p full-scale level required by the ADC. The ADL5535 low noise figure (3.2 dB at 190 MHz) and low distortion ensure that the ADC performance is not compromised. The ADL5536 can be used where a gain of 20 dB is required.

This circuit is a flexible, frequency agile IF-to-baseband receiver. Variable gain at both IF and baseband is used to adjust the signal level. The ADRF6510 baseband ADC driver also includes a programmable low-pass filter that eliminates out-of-channel blockers and noise.

The bandwidth of this filter can be dynamically adjusted as the bandwidth of the input signal changes. This ensures that the available dynamic range of the ADC that this circuit drives is fully used.

The core of the circuit is an IQ demodulator. The 2×LO based phase-splitting architecture of the ADL5387 allows for operation over a wide frequency range. Precise quadrature balance and low output dc offsets ensure that there is minimal degradation of the error vector magnitude (EVM).

The interfaces between all of the components in this circuit are fully differential. Where dc coupling is required between stages, the bias levels of the adjacent stages are compatible with each other.

The circuit shown in Figure 1 is an RF power measurement circuit that accurately measures the power from an RF signal source within a frequency range of 9 kHz to 6 GHz, and has a nominal input power range of 45 dBm (−30 dBm to +15 dBm).

This circuit constitutes a complete rms RF power meter in a tiny form factor that can be powered entirely from a 5 V USB power supply. The measurement signal chain consists of an rms responding RF power detector and a 12-bit, precision analog-to-digital converter (ADC). These devices are powered by a CMOS linear regulator which generates 3.3 V from the 5 V USB supply.

A simple calibration routine can be performed at multiple frequencies to compensate for any frequency response variation of the circuit. Calibration data is stored in a lookup table, which is referenced during the RF power measurement.

The circuit in Figure 1 is a true rms responding power detector using a variable gain amplifier (VGA) and an rms-responding power detector to provide an extremely wide detection range of approximately 95 dB. RMS detectors are useful in many applications such as receivers and transmitters where accurate measurement of signal power is required. Because the circuit measures rms power, it is suitable for use in systems with diverse or varying crest factors. Examples of such systems include GSM/EDGE, CDMA, WCDMA, TD-SCDMA and LTE based wireless base stations along with any system that uses QAM modulation.

The detection range of the ADL5902 rms detector is 65 dB and is extended to 95 dB by the addition of the linear-in-dB AD8368 VGA. The ADL5902 TADJ function is used to provide temperature stability for the complete circuit. A SAW filter is placed between the VGA to reduce noise and increase sensitivity. This also reduces the frequency range of the circuit to the pass-band range of the SAW filter.

This circuit is a flexible, frequency agile, direct conversion IF-to-baseband receiver. A fixed conversion gain of 5 dB reduces the cascaded noise figure. Variable baseband gain is used to adjust the signal level. The baseband ADC driver also includes a programmable low-pass filter that eliminates out-of-channel blockers and noise.

The bandwidth of this filter can be dynamically adjusted as the bandwidth of the input signal changes. This ensures that the available dynamic range of the ADC that this circuit drives is fully used.

The core of the circuit is an integrated IQ demodulator with fractional-N PLL and VCO. With just one (variable) reference frequency, the PLL/VCO can provide and a local oscillator (LO) between 750 MHz and 1150 MHz. Precise quadrature balance and low output dc offsets ensure that there is minimal degradation of the error vector magnitude (EVM).

The interfaces between all of the components in this circuit are fully differential. Where dc coupling is required between stages, the bias levels of the adjacent stages are compatible with each other.

The circuit, shown in Figure 1, is a 65 MHz bandwidth receiver front end based on the ADL5565 ultrahigh dynamic range differential amplifier driver and the 11-bit, 200 MSPS AD6657A quad IF receiver.

The fourth-order Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and IF receiver. The total insertion loss due the filter network and other resistive components is only 2.0 dB. The overall circuit has a bandwidth of 65 MHz, with the low-pass filter having a 1 dB bandwidth of 190 MHz and a 3 dB bandwidth of 210 MHz. The pass-band flatness is 1dB.

The circuit is optimized to process a 65 MHz bandwidth IF signal centered at 140 MHz with a sampling rate of 184.32 MSPS. The SNR and SFDR measured with a 140 MHz analog input across the 65 MHz band are 70.1 dBFS and 80.9 dBc, respectively.

The circuit shown in Figure 1 is a 16-bit, 250 MSPS, narrow-band, high IF receiver front end with an optimum interface between the ADL5565 differential amplifier and the AD9467 ADC.

The AD9467 is a buffered input 16-bit, 200 MSPS or 250 MSPS ADC with SNR performance of approximately 75.5 dBFS and SFDR performance between 95 dBFS and 98 dBFS. The ADL5565 differential amplifier is suitable for driving IF sampling ADCs because of its high input bandwidth, low distortion, and high output linearity.

This circuit note describes a systematic procedure for designing the interface circuit and the antialiasing filter that maintains high performance and ensures minimal signal loss. A resonant approach is used to design a maximally flat Butterworth fourth-order band-pass filter with a center frequency of 200 MHz.

The circuit, shown in Figure 1, is a wideband receiver front end based on the ADA4960-1 ultralow noise differential amplifier driver and the AD9434 12-bit, 500 MSPS analog-to-digital converter.

The third-order Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and ADC. The total insertion loss due to the filter network, transformer, and other resistive components is only 1.2 dB.

The overall circuit has a bandwidth of 290 MHz with a pass-band flatness of 1 dB. The SNR and SFDR measured with a 140 MHz analog input are 64.1 dBFS and 70.4 dBc, respectively.

The circuit, shown in Figure 1, is a wideband receiver front end based on the the ADL5562 ultralow noise differential amplifier driver and the AD9467 16-bit, 250 MSPS analog-to-digital converter.

The third-order Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and ADC. The total insertion loss due to the filter network and other components is only 1.8 dB.

The overall circuit has a bandwidth of 152 MHz with a pass band flatness of 1 dB. The SNR and SFDR measured with a 120 MHz analog input are 72.6 dBFS and 82.2 dBc, respectively.

The circuit, shown in Figure 1, highlights the ease of interfacing the ADF4350 wideband synthesizer with integrated VCO with the ADL5380 and ADL5387 wideband I/Q demodulators. In this circuit, the ADF4350 provides the high frequency, low phase noise local oscillator (LO) signal to the wideband I/Q demodulator.

This circuit configuration offers quite a few benefits that make it an attractive solution in applications requiring quadrature mixing down to baseband or to an intermediate frequency.

The ADF4350 offers RF differential outputs and, likewise, the ADL5380/ADL5387 accept differential inputs. This interface offers both ease of use and performance advantages. The differential signal configuration provides common-mode noise reduction and even order cancellation of the LO harmonics, which maintains the quadrature accuracy of the I/Q demodulators. Additionally, the output power level of the ADF4350 matches the input power requirements of the quadrature demodulators very well. As a result, an LO buffer is not necessary.

The ADF4350 outputs cover a wide frequency range from 137.5 MHz to 4400 MHz. The ADL5387 frequency range spans from 50 MHz to 2 GHz, and the ADL5380 covers the higher frequency range from 400 MHz to 6 GHz. Between the ADL5380 and ADL5387 the RF input range can span from 50 MHz to 6 GHz. Therefore, the two chip circuit configuration as shown in Figure 1 offers coverage of a wide frequency range from 50 MHz to 4400 GHz.

This circuit provides a simple and flexible interface between the AD9122 dual high speed TxDAC digital-to-analog converter and the ADL5375-05 broadband I/Q modulator. Because the DAC outputs and ADL5375-05 I/Q modulator inputs share a common bias level of 0.5 V, there is no need for any active or passive level shifting circuitry. The dc coupled interface facilitates I/Q modulator local oscillator (LO) leakage compensation by the DAC.

The 1.2 GSPS AD9122 DAC sampling rate and the wide bandwidth of the ADL5375-05 modulator I and Q inputs ensure that both zero-IF (ZIF) or complex-IF (CIF) architectures can be supported. In addition to filtering Nyquist images, the baseband filter provides excellent rejection of both differential-mode and common-mode DAC spurs.

The function of the circuit, shown in Figure 1, is to route an RF signal through an IF band-pass filter bank. The circuit uses three 140 MHz IF SAW filters with different bandwidths and two ADG904-R SP4T CMOS RF switches. The ADG904-R switches control which band-pass filter the RF signal will pass through. Only one filter is selectable at a time. The typical name given to this type of switching is “filter bank switching.” This application is very common in wireless infrastructure applications, such as cell phone base stations and point-topoint radio RF front ends. Selecting IF filters with different bandwidths results in more flexibility in controlling the various data rates in these systems.

Insertion loss versus frequency in the IF band must be flat to achieve optimum system performance. The ADG904-R switch is ideally suited for this circuit because it has very flat insertion loss versus frequency. The insertion loss also remains flat over the supply voltage and temperature range. Switch off isolation is another very important parameter to maximize the performance of this circuit. The ADG904-R has excellent off isolation of greater than −50 dB up to 200 MHz.

The combination of the ADRF6702 IQ modulator and the AD9122 16-bit dual 1.2 GSPS TxDAC has the dynamic range necessary for a modern high level QAM or OFDM based wireless transmitter as shown in Figure 1. The dynamic range of this circuit is good enough to enable both ZIF (zero IF/baseband) and CIF (complex IF up to 200 MHz to 300 MHz). The AD9122 has the option of up to 8× interpolation, as well as a 32-bit NCO for very fine IF frequency selectivity.

Overall performance of a transmitter is highly dependent on the dynamic range of the components directly in the signal chain. In a mixed-signal transmitter using a DAC and IQ modulator, the noise floor and distortion characteristics of these components define the overall dynamic range of the signal chain. However, the noise floor of the DAC can also be degraded by sample clock jitter, and the IQ modulator performance is dependent on the noise and spur characteristics of its local oscillator (LO). Using high performance components for sample clock and LO generation is, therefore, key to a high performance transmitter.

In addition, generating these signals physically close to the DAC and modulator on the PCB and using a single external reference can make the design much simpler. Generating the sample clock and LO (LO is very often a multi-GHz signal) separately and at some distance from the DAC and IQ modulator requires great care in the PCB layout. Subtle layout errors can cause coupling to and from these critical signals and degrade overall signal chain performance.

The signal chain performance is also heavily dependent on the DAC/ IQ modulator interface filter. For optimal performance, this passive filter should be designed after careful analysis of the required system specifications.

The ADRF6702 includes an on-board fractional PLL for LO generation so that a low frequency reference (typically less than 100 MHz) is all that is necessary to synthesize the IQ modulator LO. Using the PLL in the AD9516 clock generator allows a single reference to generate both the DAC sample clock and the PLL reference for the ADRF6702.

The circuit in Figure 1 was built using the AD9516-0, but other members of the AD9516 family could be used depending on the desired internal VCO frequency.

The circuit shown in Figure 1 measures peak and rms power at any RF frequency from 450 MHz to 6 GHz over a range of approximately 45 dB. The measurement results are converted to differential signals in order to eliminate noise and are provided as digital codes at the output of a 12-bit SAR ADC with serial interface and integrated reference. A simple twopoint calibration is performed in the digital domain.

The ADL5502 is a mean-responding (true rms) power detector in combination with an envelope detector to accurately determine the crest factor (CF) of a modulated signal. It can be used in high frequency receiver and transmitter signal chains from 450 MHz to 6 GHz with envelope bandwidths over 10 MHz. The peak-hold function allows the capture of short peaks in the envelope with lower sampling rate ADCs. Total current consumption is only 3 mA @ 3 V.

The ADA4891-4 is a high speed, quad, CMOS amplifier that offers high performance at a low cost. Current consumption is only 4.4 mA/amplifier at 3 V. The amplifier features true singlesupply capability, with an input voltage range that extends 300 mV below the negative rail. The rail-to-rail output stage enables the output to swing to within 50 mV of each rail, ensuring maximum dynamic range. Low distortion and fast settling time makes it ideal for this application.

The AD7266 is a dual, 12-bit, high speed, low power, successive approximation ADC that operates from a single 2.7 V to 5.25 V power supply and features sampling rates up to 2 MSPS. The device contains two ADCs, each preceded by a 3-channel multiplexer, and a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 30 MHz. Current consumption is only 3 mA at 3 V. It also contains an internal 2.5 V reference.

The circuit operates on a single +3.3 V supply from the ADP121, a low quiescent current, low dropout, linear regulator that operates from 2.3 V to 5.5 V and provides up to 150 mA of output current. The low 135 mV dropout voltage at 150 mA load improves efficiency and allows operation over a wide input voltage range. The low 30 μA of quiescent current at full load makes the ADP121 ideal for battery-operated portable equipment.

The ADP121 is available in output voltages ranging from 1.2 V to 3.3 V. The parts are optimized for stable operation with small 1 μF ceramic output capacitors. The ADP121 delivers good transient performance with minimal board area. Short-circuit protection and thermal overload protection circuits prevent damage in adverse conditions. The ADP121 is available in tiny 5-lead TSOT and 4-ball, 0.4 mm pitch halidefree WLCSP packages and utilizes the smallest footprint solution to meet a variety of portable applications.

This circuit provides a half-duplex, isolated RS-485 interface using the ADM2485 high speed, isolated RS-485 transceiver and the ADP3330 high accuracy linear regulator. This circuit achieves signal and power isolation and at the same time decreases board space and power consumption.

The circuit, shown in Figure 1, is a 75 MHz bandwidth receiver front end based on the ADL5202 wide dynamic range, high speed, digitally controlled variable gain amplifier (VGA) and the 14-bit, 250 MSPS AD9643 dual analog-to-digital converter (ADC).

The fifth-order Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and the ADC. The total insertion loss due to the filter network and other resistive components is approximately 2.3 dB. The overall circuit with the band-pass filter has a 1 dB bandwidth of 75 MHz (from 145 MHz to 220 MHz) and a 3 dB bandwidth of 110 MHz (from 120 MHz to 230 MHz). The pass-band flatness is 1 dB.

The circuit is optimized to process a 75 MHz bandwidth IF signal centered at 182.5 MHz (second Nyquist zone) with a sampling rate of 245.76 MSPS. The signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) measured with a 182.5 MHz analog input across the 75 MHz band are 68.4 dBFS and 80.7 dBc, respectively.

The circuit, shown in Figure 1, is a narrow, band-pass receiver front end based on the ADL5565 ultralow noise differential amplifier driver and the AD9642 14-bit, 250 MSPS analog-to-digital converter (ADC).

The third-order, Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and ADC. The total insertion loss due to the filter network and other components is only 5.8 dB.

The overall circuit has a bandwidth of 18 MHz with a pass-band flatness of 3 dB. The signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) measured with a 127 MHz analog input are 71.7 dBFS and 92 dBc, respectively. The sampling frequency is 205 MSPS, thereby positioning the IF input signal in the second Nyquist zone between 102.5 MHz and 205 MHz.

Many systems require low jitter multiple system clocks for mixed signal processing and timing. The circuit shown in Figure 1 interfaces the ADF4351 integrated phase-locked loop (PLL) and voltage-controlled oscillator (VCO) to the ADCLK948, which provides up to eight differential, low voltage, positive emitter coupled logic (LVPECL) outputs from one differential output of the ADF4351.

Modern digital systems often require many high quality clocks at logic levels that are different from the logic level of the clock source. Extra buffering may be required to guarantee accurate distribution to other circuit components without loss of integrity. The interface between the ADF4351 clock source ADCLK948 clock fanout buffer is described, and measurements show that the additive jitter associated with the clock fanout buffer is 75 fs rms.

The circuit shown in Figure 1 solves a problem often encountered in dc-coupled single-supply systems when interfacing bipolar input signals to differential input, low voltage analog-to-digital converters (ADCs). The technique ensures the proper common-mode voltage level at the input to the differential drive amplifier by controlling the input common-mode level using two level shifting resistors. The output common-mode voltage is established independently by applying the correct voltage to the VOCM pin of the ADA4930-1 differential driver.

This flexible arrangement allows the ADA4930-1 differential driver to operate on a single 3.3 V supply, while the AD9265 16-bit 125 MSPS ADC operates on a 1.8 V supply, thereby minimizing the total circuit power dissipation.

In broadband applications, the frequency range of interest often includes dc. To maximize the dynamic range of a differential input ADC, typical input signals can be relatively large, thereby requiring the differential driver to operate at lower gain settings. Under these conditions, the input common-mode voltage of the differential driver must stay within the specified range.

Independent control of the input and output common-mode voltage of differential amplifiers is often required in direct coupled single-supply applications such as processing demodulator outputs with high input common-mode voltages, x-ray applications with a dc component added to a differential component, and other places where the differential driver must handle low value input common-mode voltages. Low input common-mode voltage applications can include either single-ended or differential inputs, with zero, bipolar, or negative inputs.

This circuit is a complete implementation of the analog portion of a broadband direct conversion transmitter (analog baseband in, RF out). RF frequencies from 500 MHz to 4.4 GHz are supported through the use of a PLL with a broadband integrated voltage controlled oscillator (VCO). Harmonic filtering of the LO from the PLL ensures excellent quadrature accuracy.

Low noise LDOs ensure that the power management scheme has no adverse impact on phase noise and EVM. This combination of components represents industry-leading direct conversion transmitter performance over a frequency range of 500 MHz to 4.4 GHz.

The circuit block diagram shown in Figure 1 is a low phase noise translation loop synthesizer (also known as an offset loop). This circuit translates the lower 100 MHz reference frequency of the ADF4002 phase locked loop (PLL) up to a higher frequency range of 5.0 GHz to 5.4 GHz, as determined by the frequency of the local oscillator (LO).

The translation loop synthesizer has very low phase noise (<50 fs) in contrast to a synthesizer using only a PLL. The low phase noise is because of the very low N value used by the ADF4002 integer-N PLL, which controls the voltage controlled oscillator (VCO). In this example, the ADF4002 phase frequency detector (PFD) runs at 100 MHz, and N = 1, yielding phase noise performance that is not limited by the N value of the PLL.

The circuit shown in Figure 1 accurately measures return loss in a wireless transmitter from 1 GHz to 28 GHz without any need for system calibration.

The design is implemented on a single circuit board using a nonreflective RF switch; a microwave RF detector; and a 12-bit, precision analog-to-digital converter (ADC). To evaluate the circuit over the widest possible frequency range, a dual-port directional coupler with SMA connectors was used instead of a narrow-band, surface-mount directional coupler.

The circuit measures return loss of up to 20 dB over an input power range of 25 dB (return losses in excess of 20 dB can be measured over a smaller input power range).

A unique feature of the circuit is that it calculates return loss using a simple ratio of the digitized voltages from the RF detector, thereby eliminating the need for system calibration.